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-rw-r--r--src/soc/amd/picasso/include/soc/iomap.h1
-rw-r--r--src/soc/amd/picasso/include/soc/pci_devs.h7
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h5
3 files changed, 0 insertions, 13 deletions
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index ad76f3a83d..1d89fd7ec0 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -18,7 +18,6 @@
#define __SOC_PICASSO_IOMAP_H__
/* MMIO Ranges */
-#define PSP_MAILBOX_BAR3_BASE 0xf0a00000
#define SPI_BASE_ADDRESS 0xfec10000
#define IO_APIC2_ADDR 0xfec20000
diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h
index 8a885f2c0b..d6887f9b38 100644
--- a/src/soc/amd/picasso/include/soc/pci_devs.h
+++ b/src/soc/amd/picasso/include/soc/pci_devs.h
@@ -95,13 +95,6 @@
#define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC)
#define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC)
-/* Platform Security Processor */
-#define PSP_DEV 0x8
-#define PSP_FUNC 0
-#define PSP_DEVID 0x1578
-#define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC)
-#define SOC_PSP_DEV _SOC_DEV(PSP_DEV, PSP_FUNC)
-
/* HD Audio 1 */
#define HDA1_DEV 0x9
#define HDA1_FUNC 2
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 0f72a68567..b28522e60f 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -277,11 +277,6 @@
#define SPI100_HOST_PREF_CONFIG 0x2c
#define SPI_RD4DW_EN_HOST BIT(15)
-/* Platform Security Processor D8F0 */
-#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */
-#define PSP_BAR_ENABLES 0x48
-#define PSP_MAILBOX_BAR_EN 0x10
-
/* IO 0xcf9 - Reset control port*/
#define FULL_RST BIT(3)
#define RST_CMD BIT(2)