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Diffstat (limited to 'src/soc/amd/picasso/include/soc/cpu.h')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/cpu.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h new file mode 100644 index 0000000000..934a9f2983 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __STONEYRIDGE_CPU_H__ +#define __STONEYRIDGE_CPU_H__ + +#include <device/device.h> + +/* + * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest + * numbered registers. Any values defined below are subtracted from the + * highest numbered registers. + * + * todo: Revisit this once AGESA no longer programs MTRRs. + */ +#define SOC_EARLY_VMTRR_FLASH 1 +#define SOC_EARLY_VMTRR_CAR_HEAP 2 +#define SOC_EARLY_VMTRR_TEMPRAM 3 + +void stoney_init_cpus(struct device *dev); +void check_mca(void); + +#endif /* __STONEYRIDGE_CPU_H__ */ |