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-rw-r--r--src/soc/amd/phoenix/acpi.c12
-rw-r--r--src/soc/amd/phoenix/include/soc/msr.h8
2 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index 1be00f9828..4fae1c9d74 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -111,12 +111,12 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
if (core_freq_div == 0) {
return 0;
- } else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN)
- && (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) {
+ } else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
+ && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
/* Allow 1/8 integer steps for this range */
valid_freq_divisor = true;
- } else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX)
- && (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
+ } else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
+ && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
/* Only allow 1/4 integer steps for this range */
valid_freq_divisor = true;
} else {
@@ -126,11 +126,11 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
if (valid_freq_divisor) {
/* 25 * core_freq_mul / (core_freq_div / 8) */
core_freq =
- ((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
+ ((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
} else {
printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
core_freq_div);
- core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul);
+ core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
}
return core_freq;
}
diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h
index 8ac48bfd36..ef7a2e2260 100644
--- a/src/soc/amd/phoenix/include/soc/msr.h
+++ b/src/soc/amd/phoenix/include/soc/msr.h
@@ -20,10 +20,10 @@ union pstate_msr {
uint64_t raw;
};
-#define PSTATE_DEF_LO_FREQ_DIV_MIN 0x8
-#define PSTATE_DEF_LO_EIGHTH_STEP_MAX 0x1A
-#define PSTATE_DEF_LO_FREQ_DIV_MAX 0x3E
-#define PSTATE_DEF_LO_CORE_FREQ_BASE 25
+#define PSTATE_DEF_FREQ_DIV_MIN 0x8
+#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A
+#define PSTATE_DEF_FREQ_DIV_MAX 0x3E
+#define PSTATE_DEF_CORE_FREQ_BASE 25
/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
#define SERIAL_VID_DECODE_MICROVOLTS 5000