3 files changed, 1 insertions, 15 deletions
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 5e9b7f95bb..c68ee47b00 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -44,6 +44,7 @@ config SOC_AMD_GLINDA
 	select SOC_AMD_COMMON_BLOCK_APOB		# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_APOB_HASH		# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS	# TODO: Check if this is still correct
+	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
 	select SOC_AMD_COMMON_BLOCK_EMMC		# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct
diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c
index 850bc6c5af..49fb658d63 100644
--- a/src/soc/amd/glinda/acpi.c
+++ b/src/soc/amd/glinda/acpi.c
@@ -16,11 +16,9 @@
 #include <arch/smp/mpspec.h>
 #include <console/console.h>
 #include <cpu/amd/cpuid.h>
-#include <cpu/amd/msr.h>
 #include <cpu/x86/smm.h>
 #include <soc/acpi.h>
 #include <soc/iomap.h>
-#include <soc/msr.h>
 #include <types.h>
 #include "chip.h"
 
@@ -98,17 +96,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
 }
 
-uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
-{
-	uint32_t core_freq_mul;
-
-	/* Core frequency multiplier */
-	core_freq_mul = pstate_reg.cpu_fid_0_11;
-
-	/* CPU frequency is 5 * core_freq_mul */
-	return PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul;
-}
-
 const acpi_cstate_t cstate_cfg_table[] = {
 	[0] = {
 		.ctype = 1,
diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h
index ad4d9d0445..2f40d395f3 100644
--- a/src/soc/amd/glinda/include/soc/msr.h
+++ b/src/soc/amd/glinda/include/soc/msr.h
@@ -20,8 +20,6 @@ union pstate_msr {
 	uint64_t raw;
 };
 
-#define PSTATE_DEF_CORE_FREQ_BASE	5
-
 #define MSR_CPPC_CAPABILITY_1				0xc00102b0
 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF		16