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-rw-r--r--src/soc/amd/glinda/include/soc/msr.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h
index 3f9254971c..7b6889709e 100644
--- a/src/soc/amd/glinda/include/soc/msr.h
+++ b/src/soc/amd/glinda/include/soc/msr.h
@@ -23,8 +23,8 @@ union pstate_msr {
#define PSTATE_DEF_CORE_FREQ_BASE 5
/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
-#define SERIAL_VID_DECODE_MICROVOLTS 5000
-#define SERIAL_VID_BASE_MICROVOLTS 245000L
+#define SERIAL_VID_3_DECODE_MICROVOLTS 5000
+#define SERIAL_VID_3_BASE_MICROVOLTS 245000L
#define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24