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-rw-r--r--src/soc/amd/genoa_poc/chip.c7
-rw-r--r--src/soc/amd/genoa_poc/fch.c8
-rw-r--r--src/soc/amd/genoa_poc/include/soc/southbridge.h1
3 files changed, 9 insertions, 7 deletions
diff --git a/src/soc/amd/genoa_poc/chip.c b/src/soc/amd/genoa_poc/chip.c
index eb35a25bf8..5f29428955 100644
--- a/src/soc/amd/genoa_poc/chip.c
+++ b/src/soc/amd/genoa_poc/chip.c
@@ -3,10 +3,17 @@
#include <device/device.h>
#include <soc/southbridge.h>
#include <soc/acpi.h>
+#include <soc/southbridge.h>
+#include <vendorcode/amd/opensil/genoa_poc/opensil.h>
static void soc_init(void *chip_info)
{
default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
+
+ setup_opensil();
+ opensil_entry(SIL_TP1);
+
+ fch_init(chip_info);
}
static void soc_final(void *chip_info)
diff --git a/src/soc/amd/genoa_poc/fch.c b/src/soc/amd/genoa_poc/fch.c
index c9779571da..f340d82c39 100644
--- a/src/soc/amd/genoa_poc/fch.c
+++ b/src/soc/amd/genoa_poc/fch.c
@@ -81,14 +81,8 @@ static void fch_init_acpi_ports(void)
configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
}
-static void fch_init(void *unused)
+void fch_init(void *chip_info)
{
set_pci_irqs();
fch_init_acpi_ports();
}
-
-/*
- * Hook this function into the PCI state machine on entry into BS_DEV_ENABLE.
- * TODO: can this be done without using BOOT_STATE_INIT_ENTRY?
- */
-BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fch_init, NULL);
diff --git a/src/soc/amd/genoa_poc/include/soc/southbridge.h b/src/soc/amd/genoa_poc/include/soc/southbridge.h
index a761d533c3..1027a58455 100644
--- a/src/soc/amd/genoa_poc/include/soc/southbridge.h
+++ b/src/soc/amd/genoa_poc/include/soc/southbridge.h
@@ -117,5 +117,6 @@
void fch_pre_init(void);
void fch_early_init(void);
+void fch_init(void *chip_info);
#endif /* AMD_GENOA_POC_SOUTHBRIDGE_H */