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-rw-r--r--src/soc/amd/common/block/include/amdblocks/espi.h7
-rw-r--r--src/soc/amd/common/block/lpc/espi_util.c3
2 files changed, 2 insertions, 8 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h
index f5e7d31851..435b81f7e0 100644
--- a/src/soc/amd/common/block/include/amdblocks/espi.h
+++ b/src/soc/amd/common/block/include/amdblocks/espi.h
@@ -101,13 +101,6 @@ int espi_open_io_window(uint16_t base, size_t size);
int espi_open_mmio_window(uint32_t base, size_t size);
/*
- * Clear all configured eSPI memory and I/O decode ranges. This is useful for changing
- * the decodes, or if something else has previously setup decode windows that conflict
- * with the windows that coreboot needs.
- */
-void espi_clear_decodes(void);
-
-/*
* In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading
* SPIBASE. This is required for cases where verstage runs on PSP.
*/
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 0b690b821b..f120082542 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -98,7 +98,7 @@ static int espi_get_unused_io_window(void)
return -1;
}
-void espi_clear_decodes(void)
+static void espi_clear_decodes(void)
{
unsigned int idx;
@@ -894,6 +894,7 @@ int espi_setup(void)
espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI);
espi_write32(ESPI_SLAVE0_INT_EN, 0);
espi_clear_status();
+ espi_clear_decodes();
/*
* Boot sequence: Step 1