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Diffstat (limited to 'src/soc/amd/common/block/include/amdblocks/psp.h')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/psp.h20
1 files changed, 2 insertions, 18 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h
index 494f1744f0..42c802d51b 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp.h
@@ -15,24 +15,8 @@
#ifndef __AMD_PSP_H__
#define __AMD_PSP_H__
-#include <amdblocks/agesawrapper.h>
-#include <soc/pci_devs.h>
-#include <types.h>
-
-/* Extra, Special Purpose Registers in the PSP PCI Config Space */
-
-/* PSP Mirror Features Capabilities and Control Register */
-#define PSP_PCI_MIRRORCTRL1_REG 0x44 /* PSP Mirror Ctrl Reg */
-#define PMNXTPTRW_MASK 0xff /* PCI AFCR pointer mask */
-#define PMNXTPTRW_EXPOSE 0xa4 /* Pointer to expose the AFCR */
-
-#define PSP_PCI_EXT_HDR_CTRL 0x48 /* Extra PCI Header Ctrl */
-#define MAGIC_ENABLES 0x34 /* Extra PCI HDR Ctl Enables */
-
-#define PSP_MAILBOX_BASE 0x70 /* Mailbox offset from PCIe BAR */
-
-#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */
-#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */
+/* Get the mailbox base address - specific to family of device. */
+struct psp_mbox *soc_get_mbox_address(void);
/* x86 to PSP commands */
#define MBOX_BIOS_CMD_DRAM_INFO 0x01