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-rw-r--r--src/soc/amd/cezanne/include/soc/msr.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h
index ca2992a121..83357c1884 100644
--- a/src/soc/amd/cezanne/include/soc/msr.h
+++ b/src/soc/amd/cezanne/include/soc/msr.h
@@ -21,6 +21,10 @@
#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
#define PSTATE_DEF_LO_CORE_FREQ_BASE 25
+/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
+#define SERIAL_VID_DECODE_MICROVOLTS 6250
+#define SERIAL_VID_MAX_MICROVOLTS 1550000L
+
#define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24
#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16