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-rw-r--r--src/soc/amd/cezanne/Makefile.mk1
-rw-r--r--src/soc/amd/cezanne/memmap.c98
-rw-r--r--src/soc/amd/cezanne/root_complex.c96
3 files changed, 99 insertions, 96 deletions
diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk
index 163f777dab..73be4aacb0 100644
--- a/src/soc/amd/cezanne/Makefile.mk
+++ b/src/soc/amd/cezanne/Makefile.mk
@@ -25,6 +25,7 @@ ramstage-y += fch.c
ramstage-y += fsp_s_params.c
ramstage-y += graphics.c
ramstage-y += mca.c
+ramstage-y += memmap.c
ramstage-y += root_complex.c
ramstage-y += xhci.c
diff --git a/src/soc/amd/cezanne/memmap.c b/src/soc/amd/cezanne/memmap.c
new file mode 100644
index 0000000000..6c8e93221c
--- /dev/null
+++ b/src/soc/amd/cezanne/memmap.c
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/iomap.h>
+#include <amdblocks/memmap.h>
+#include <amdblocks/root_complex.h>
+#include <arch/vga.h>
+#include <cbmem.h>
+#include <device/device.h>
+#include <stdint.h>
+
+/*
+ * +--------------------------------+
+ * | |
+ * | |
+ * | |
+ * | |
+ * | |
+ * | |
+ * | |
+ * reserved_dram_end +--------------------------------+
+ * | |
+ * | verstage (if reqd) |
+ * | (VERSTAGE_SIZE) |
+ * +--------------------------------+ VERSTAGE_ADDR
+ * | |
+ * | FSP-M |
+ * | (FSP_M_SIZE) |
+ * +--------------------------------+ FSP_M_ADDR
+ * | romstage |
+ * | (ROMSTAGE_SIZE) |
+ * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
+ * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
+ * | bootblock |
+ * | (C_ENV_BOOTBLOCK_SIZE) |
+ * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
+ * | Unused hole |
+ * | (86KiB) |
+ * +--------------------------------+
+ * | FMAP cache (FMAP_SIZE) |
+ * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
+ * | Early Timestamp region (512B) |
+ * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
+ * | Preram CBMEM console |
+ * | (PRERAM_CBMEM_CONSOLE_SIZE) |
+ * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
+ * | PSP shared (vboot workbuf) |
+ * | (PSP_SHAREDMEM_SIZE) |
+ * +--------------------------------+ PSP_SHAREDMEM_BASE
+ * | APOB (64KiB) |
+ * +--------------------------------+ PSP_APOB_DRAM_ADDRESS
+ * | Early BSP stack |
+ * | (EARLYRAM_BSP_STACK_SIZE) |
+ * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
+ * | DRAM |
+ * +--------------------------------+ 0x100000
+ * | Option ROM |
+ * +--------------------------------+ 0xc0000
+ * | Legacy VGA |
+ * +--------------------------------+ 0xa0000
+ * | DRAM |
+ * +--------------------------------+ 0x0
+ */
+void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
+{
+ uint32_t mem_usable = (uintptr_t)cbmem_top();
+
+ uintptr_t early_reserved_dram_start, early_reserved_dram_end;
+ const struct memmap_early_dram *e = memmap_get_early_dram_usage();
+
+ early_reserved_dram_start = e->base;
+ early_reserved_dram_end = e->base + e->size;
+
+ /* 0x0 - 0x9ffff */
+ ram_range(dev, (*idx)++, 0, 0xa0000);
+
+ /* 0xa0000 - 0xbffff: legacy VGA */
+ mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
+
+ /* 0xc0000 - 0xfffff: Option ROM */
+ reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
+
+ /* 1MiB - bottom of DRAM reserved for early coreboot usage */
+ ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
+
+ /* DRAM reserved for early coreboot usage */
+ reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
+
+ /*
+ * top of DRAM consumed early - low top usable RAM
+ * cbmem_top() accounts for low UMA and TSEG if they are used.
+ */
+ ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
+
+ /* Reserve fixed IOMMU MMIO region */
+ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
+
+ read_fsp_resources(dev, idx);
+}
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index 876f790718..0fb086fc50 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -1,17 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpigen.h>
-#include <amdblocks/acpi.h>
#include <amdblocks/alib.h>
#include <amdblocks/data_fabric.h>
#include <amdblocks/ioapic.h>
-#include <amdblocks/iomap.h>
-#include <amdblocks/memmap.h>
#include <amdblocks/root_complex.h>
#include <arch/ioapic.h>
-#include <arch/vga.h>
-#include <cbmem.h>
-#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <soc/iomap.h>
@@ -48,96 +42,6 @@ struct dptc_input {
}, \
}
-/*
- *
- * +--------------------------------+
- * | |
- * | |
- * | |
- * | |
- * | |
- * | |
- * | |
- * reserved_dram_end +--------------------------------+
- * | |
- * | verstage (if reqd) |
- * | (VERSTAGE_SIZE) |
- * +--------------------------------+ VERSTAGE_ADDR
- * | |
- * | FSP-M |
- * | (FSP_M_SIZE) |
- * +--------------------------------+ FSP_M_ADDR
- * | romstage |
- * | (ROMSTAGE_SIZE) |
- * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
- * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
- * | bootblock |
- * | (C_ENV_BOOTBLOCK_SIZE) |
- * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
- * | Unused hole |
- * | (86KiB) |
- * +--------------------------------+
- * | FMAP cache (FMAP_SIZE) |
- * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
- * | Early Timestamp region (512B) |
- * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
- * | Preram CBMEM console |
- * | (PRERAM_CBMEM_CONSOLE_SIZE) |
- * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
- * | PSP shared (vboot workbuf) |
- * | (PSP_SHAREDMEM_SIZE) |
- * +--------------------------------+ PSP_SHAREDMEM_BASE
- * | APOB (64KiB) |
- * +--------------------------------+ PSP_APOB_DRAM_ADDRESS
- * | Early BSP stack |
- * | (EARLYRAM_BSP_STACK_SIZE) |
- * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
- * | DRAM |
- * +--------------------------------+ 0x100000
- * | Option ROM |
- * +--------------------------------+ 0xc0000
- * | Legacy VGA |
- * +--------------------------------+ 0xa0000
- * | DRAM |
- * +--------------------------------+ 0x0
- */
-void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
-{
- uint32_t mem_usable = (uintptr_t)cbmem_top();
-
- uintptr_t early_reserved_dram_start, early_reserved_dram_end;
- const struct memmap_early_dram *e = memmap_get_early_dram_usage();
-
- early_reserved_dram_start = e->base;
- early_reserved_dram_end = e->base + e->size;
-
- /* 0x0 - 0x9ffff */
- ram_range(dev, (*idx)++, 0, 0xa0000);
-
- /* 0xa0000 - 0xbffff: legacy VGA */
- mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
-
- /* 0xc0000 - 0xfffff: Option ROM */
- reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
-
- /* 1MiB - bottom of DRAM reserved for early coreboot usage */
- ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
-
- /* DRAM reserved for early coreboot usage */
- reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
-
- /*
- * top of DRAM consumed early - low top usable RAM
- * cbmem_top() accounts for low UMA and TSEG if they are used.
- */
- ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
-
- /* Reserve fixed IOMMU MMIO region */
- mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
-
- read_fsp_resources(dev, idx);
-}
-
static void root_complex_init(struct device *dev)
{
register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 08:15:31 +0000