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-rw-r--r--src/soc/amd/cezanne/Kconfig1
-rw-r--r--src/soc/amd/cezanne/Makefile.inc1
-rw-r--r--src/soc/amd/cezanne/romstage.c28
3 files changed, 1 insertions, 29 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 42a7bf335e..0ef658c10f 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -77,6 +77,7 @@ config SOC_AMD_CEZANNE
select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SOC_AMD_COMMON_BLOCK_XHCI
+ select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
select SSE2
select UDK_2017_BINDING
select USE_DDR4
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 044d33ead2..dedf98c4bd 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -17,7 +17,6 @@ bootblock-y += early_fch.c
bootblock-y += espi_util.c
romstage-y += fsp_m_params.c
-romstage-y += romstage.c
ramstage-y += acpi.c
ramstage-y += agesa_acpi.c
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
deleted file mode 100644
index 6b84728ad1..0000000000
--- a/src/soc/amd/cezanne/romstage.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/fsp.h>
-#include <amdblocks/memmap.h>
-#include <amdblocks/pmlib.h>
-#include <amdblocks/post_codes.h>
-#include <console/console.h>
-#include <cpu/cpu.h>
-#include <program_loading.h>
-#include <romstage_common.h>
-
-void __noreturn romstage_main(void)
-{
- post_code(POSTCODE_ROMSTAGE_MAIN);
-
- /* Snapshot chipset state prior to any FSP call */
- fill_chipset_state();
-
- amd_fsp_early_init();
-
- /* Fixup settings FSP-M should not be changing */
- fch_disable_legacy_dma_io();
-
- memmap_stash_early_dram_usage();
-
- run_ramstage();
-}