diff options
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/acpi.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/msr.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index f65973d979..43ed7fed05 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -150,8 +150,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg) /* Voltage off for VID codes 0xF8 to 0xFF */ voltage_in_uvolts = 0; } else { - voltage_in_uvolts = - SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid); + voltage_in_uvolts = SERIAL_VID_2_MAX_MICROVOLTS - + (SERIAL_VID_2_DECODE_MICROVOLTS * core_vid); } /* Power in mW */ diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index 2ce03ade8a..fdbe47e342 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -23,8 +23,8 @@ union pstate_msr { #define PSTATE_DEF_CORE_FREQ_BASE 25 /* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ -#define SERIAL_VID_DECODE_MICROVOLTS 6250 -#define SERIAL_VID_MAX_MICROVOLTS 1550000L +#define SERIAL_VID_2_DECODE_MICROVOLTS 6250 +#define SERIAL_VID_2_MAX_MICROVOLTS 1550000L #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 |