diff options
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/acpi.c | 8 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/msr.h | 4 |
3 files changed, 2 insertions, 11 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 046fd233f4..dbb628bfff 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -63,6 +63,7 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY select SOC_AMD_COMMON_BLOCK_SPI + select SOC_AMD_COMMON_BLOCK_SVI2 select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 43ed7fed05..cebdf7c5b9 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -146,13 +146,7 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg) current_divisor = pstate_reg.idd_div; /* Voltage */ - if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) { - /* Voltage off for VID codes 0xF8 to 0xFF */ - voltage_in_uvolts = 0; - } else { - voltage_in_uvolts = SERIAL_VID_2_MAX_MICROVOLTS - - (SERIAL_VID_2_DECODE_MICROVOLTS * core_vid); - } + voltage_in_uvolts = get_uvolts_from_vid(core_vid); /* Power in mW */ power_in_mw = (voltage_in_uvolts) / 10 * current_value_amps; diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index fdbe47e342..79ebc7eee5 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -22,10 +22,6 @@ union pstate_msr { #define PSTATE_DEF_FREQ_DIV_MAX 0x3E #define PSTATE_DEF_CORE_FREQ_BASE 25 -/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ -#define SERIAL_VID_2_DECODE_MICROVOLTS 6250 -#define SERIAL_VID_2_MAX_MICROVOLTS 1550000L - #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 |