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Diffstat (limited to 'src/soc/amd/cezanne/romstage.c')
-rw-r--r--src/soc/amd/cezanne/romstage.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 509addfa52..f790def747 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <fsp/api.h>
@@ -19,7 +20,7 @@ asmlinkage void car_stage_entry(void)
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
- fsp_memory_init(false); /* no S3 resume yet */
+ fsp_memory_init(acpi_is_wakeup_s3());
run_ramstage();
}