diff options
Diffstat (limited to 'src/soc/amd/cezanne/include')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/cppc.h | 12 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/msr.h | 18 |
2 files changed, 30 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/cppc.h b/src/soc/amd/cezanne/include/soc/cppc.h new file mode 100644 index 0000000000..60a5efd334 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/cppc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CPU_AMD_COMMON_H +#define _CPU_AMD_COMMON_H + +#include <types.h> + +struct cppc_config; +void cpu_init_cppc_config(struct cppc_config *config, u32 version); +void generate_cppc_entries(unsigned int core_id); + +#endif diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index cc1f77e35b..ca2992a121 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -21,4 +21,22 @@ #define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25 +#define MSR_CPPC_CAPABILITY_1 0xc00102b0 +#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 +#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 +#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 +#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 + +#define MSR_CPPC_ENABLE 0xc00102b1 +#define MSR_CPPC_REQUEST 0xc00102b3 +#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 +#define SHIFT_CPPC_REQUEST_DES_PERF 16 +#define SHIFT_CPPC_REQUEST_MIN_PERF 8 +#define SHIFT_CPPC_REQUEST_MAX_PERF 0 + +#define MSR_CPPC_STATUS 0xc00102b4 + +#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 +#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 + #endif /* AMD_CEZANNE_MSR_H */ |