3 files changed, 18 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index 96313eaf3c..4d47f7ed57 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -4,6 +4,7 @@
 #define AMD_CEZANNE_IOMAP_H
 
 /* I/O Ranges */
-#define SMB_BASE_ADDR			0xb00
+#define NCP_ERR				0x00f0
+#define SMB_BASE_ADDR			0x0b00
 
 #endif /* AMD_CEZANNE_IOMAP_H */
diff --git a/src/soc/amd/cezanne/include/soc/reset.h b/src/soc/amd/cezanne/include/soc/reset.h
new file mode 100644
index 0000000000..4cb94ced02
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/reset.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_RESET_H
+#define AMD_CEZANNE_RESET_H
+
+void set_warm_reset_flag(void);
+int is_warm_reset(void);
+
+#endif /* AMD_CEZANNE_RESET_H */
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 2456ebc6f9..03ee2bb2d1 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -5,6 +5,13 @@
 
 #include <soc/iomap.h>
 
+/* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
+#define PWR_RESET_CFG			0x10
+#define   TOGGLE_ALL_PWR_GOOD		(1 << 1)
+
+/* IO 0xf0 NCP Error */
+#define   NCP_WARM_BOOT			(1 << 7) /* Write-once */
+
 void fch_pre_init(void);
 void fch_early_init(void);