diff options
Diffstat (limited to 'src/soc/amd/cezanne/i2c.c')
| -rw-r--r-- | src/soc/amd/cezanne/i2c.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c index ae49a064e0..98e2413ee9 100644 --- a/src/soc/amd/cezanne/i2c.c +++ b/src/soc/amd/cezanne/i2c.c @@ -6,6 +6,14 @@ #include <soc/southbridge.h> #include "chip.h" +/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ +static const struct soc_i2c_scl_pin i2c_scl_pins[] = { + I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), + I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), +}; + #if ENV_X86 static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" }, @@ -32,6 +40,17 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar) } #endif +void reset_i2c_peripherals(void) +{ + const struct soc_amd_cezanne_config *cfg = config_of_soc(); + struct soc_i2c_peripheral_reset_info reset_info; + + reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; + reset_info.i2c_scl = i2c_scl_pins; + reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); + sb_reset_i2c_peripherals(&reset_info); +} + void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { const struct soc_amd_cezanne_config *config = config_of_soc(); |