diff options
Diffstat (limited to 'src/soc/amd/cezanne/fch.c')
| -rw-r--r-- | src/soc/amd/cezanne/fch.c | 40 |
1 files changed, 1 insertions, 39 deletions
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index f065c8e454..1abe00dd1a 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -135,45 +135,7 @@ static void fch_init_acpi_ports(void) static void gpp_clk_setup(void) { struct soc_amd_cezanne_config *cfg = config_of_soc(); - - /* look-up table to be able to iterate over the PCIe clock output settings */ - const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { - GPP_CLK0_REQ_SHIFT, - GPP_CLK1_REQ_SHIFT, - GPP_CLK2_REQ_SHIFT, - GPP_CLK3_REQ_SHIFT, - GPP_CLK4_REQ_SHIFT, - GPP_CLK5_REQ_SHIFT, - GPP_CLK6_REQ_SHIFT, - }; - - uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); - - pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], - ARRAY_SIZE(cfg->gpp_clk_config)); - for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { - gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); - - /* - * The remapping of values is done so that the default of the enum used for the - * devicetree settings is the clock being enabled, so that a missing devicetree - * configuration for this will result in an always active clock and not an - * inactive PCIe clock output. - */ - switch (cfg->gpp_clk_config[i]) { - case GPP_CLK_REQ: - gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); - break; - case GPP_CLK_OFF: - gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]); - break; - case GPP_CLK_ON: - default: - gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]); - } - } - - misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); + gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config)); } static void cgpll_clock_gate_init(void) |