diff options
Diffstat (limited to 'src/soc/amd/cezanne/chip.h')
-rw-r--r-- | src/soc/amd/cezanne/chip.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index af78ddfd9a..7753ab8623 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -27,6 +27,45 @@ struct soc_amd_cezanne_config { DOWNCORE_7 = 10, /* Run with 7 physical cores */ } downcore_mode; bool disable_smt; /* disable second thread on all physical cores */ + + uint8_t stt_control; + uint8_t stt_pcb_sensor_count; + uint16_t stt_min_limit; + uint16_t stt_m1; + uint16_t stt_m2; + uint16_t stt_m3; + uint16_t stt_m4; + uint16_t stt_m5; + uint16_t stt_m6; + uint16_t stt_c_apu; + uint16_t stt_c_gpu; + uint16_t stt_c_hs2; + uint16_t stt_alpha_apu; + uint16_t stt_alpha_gpu; + uint16_t stt_alpha_hs2; + uint16_t stt_skin_temp_apu; + uint16_t stt_skin_temp_gpu; + uint16_t stt_skin_temp_hs2; + uint16_t stt_error_coeff; + uint16_t stt_error_rate_coefficient; + + uint8_t stapm_boost; + uint32_t stapm_time_constant; + uint32_t apu_only_sppt_limit; + uint32_t sustained_power_limit; + uint32_t fast_ppt_limit; + uint32_t slow_ppt_limit; + + uint8_t smartshift_enable; + + uint8_t system_configuration; + + uint8_t cppc_ctrl; + uint8_t cppc_perf_limit_max_range; + uint8_t cppc_perf_limit_min_range; + uint8_t cppc_epp_max_range; + uint8_t cppc_epp_min_range; + uint8_t cppc_preferred_cores; }; #endif /* CEZANNE_CHIP_H */ |