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-rw-r--r--src/northbridge/intel/gm45/gma.c46
-rw-r--r--src/northbridge/intel/haswell/gma.c44
-rw-r--r--src/northbridge/intel/i945/gma.c46
-rw-r--r--src/northbridge/intel/ironlake/gma.c45
-rw-r--r--src/northbridge/intel/pineview/gma.c45
-rw-r--r--src/northbridge/intel/sandybridge/gma.c44
-rw-r--r--src/northbridge/intel/x4x/gma.c51
7 files changed, 14 insertions, 307 deletions
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 0c97b64b39..e9bd722da9 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -11,8 +11,6 @@
#include <string.h>
#include <device/pci_ops.h>
#include <commonlib/helpers.h>
-#include <cbmem.h>
-#include <southbridge/intel/i82801ix/nvs.h>
#include <types.h>
#include "drivers/intel/gma/i915_reg.h"
@@ -31,19 +29,6 @@ void gtt_write(u32 reg, u32 data)
write32(res2mmio(gtt_res, reg, 0), data);
}
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
- const global_nvs_t *gnvs_ptr = gnvs;
- return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
- global_nvs_t *gnvs_ptr = gnvs;
- if (gnvs_ptr)
- gnvs_ptr->aslb = aslb;
-}
-
static u32 get_cdclk(struct device *const dev)
{
const u16 cdclk_sel =
@@ -165,6 +150,8 @@ static void gma_func0_init(struct device *dev)
struct edid edid_lvds;
const struct northbridge_intel_gm45_config *const conf = dev->chip_info;
+ intel_gma_init_igd_opregion();
+
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
@@ -203,8 +190,6 @@ static void gma_func0_init(struct device *dev)
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA");
}
}
-
- intel_gma_restore_opregion();
}
static void gma_generate_ssdt(const struct device *device)
@@ -214,32 +199,6 @@ static void gma_generate_ssdt(const struct device *device)
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
-static unsigned long
-gma_write_acpi_tables(const struct device *const dev,
- unsigned long current,
- struct acpi_rsdp *const rsdp)
-{
- igd_opregion_t *opregion = (igd_opregion_t *)current;
- global_nvs_t *gnvs;
-
- if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
- return current;
-
- current += sizeof(igd_opregion_t);
-
- /* GNVS has been already set up */
- gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
- if (gnvs) {
- /* IGD OpRegion Base Address */
- gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
- } else {
- printk(BIOS_ERR, "Error: GNVS table not found.\n");
- }
-
- current = acpi_align_current(current);
- return current;
-}
-
static const char *gma_acpi_name(const struct device *dev)
{
return "GFX0";
@@ -257,7 +216,6 @@ static struct device_operations gma_func0_ops = {
.init = gma_func0_init,
.ops_pci = &gma_pci_ops,
.acpi_name = gma_acpi_name,
- .write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short pci_device_ids[] =
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 0caa64fe11..ae9e25704d 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -4,7 +4,6 @@
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
-#include <cbmem.h>
#include <console/console.h>
#include <bootmode.h>
#include <delay.h>
@@ -16,7 +15,6 @@
#include <drivers/intel/gma/libgfxinit.h>
#include <cpu/intel/haswell/haswell.h>
#include <drivers/intel/gma/opregion.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
#include <string.h>
#include <types.h>
@@ -209,19 +207,6 @@ int gtt_poll(u32 reg, u32 mask, u32 value)
return 0;
}
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
- const global_nvs_t *gnvs_ptr = gnvs;
- return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
- global_nvs_t *gnvs_ptr = gnvs;
- if (gnvs_ptr)
- gnvs_ptr->aslb = aslb;
-}
-
static void power_well_enable(void)
{
gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE);
@@ -475,6 +460,8 @@ static void gma_func0_init(struct device *dev)
int lightup_ok = 0;
u32 reg32;
+ intel_gma_init_igd_opregion();
+
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
@@ -509,7 +496,6 @@ static void gma_func0_init(struct device *dev)
gma_pm_init_post_vbios(dev);
gma_enable_swsci();
- intel_gma_restore_opregion();
}
static void gma_generate_ssdt(const struct device *dev)
@@ -519,31 +505,6 @@ static void gma_generate_ssdt(const struct device *dev)
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
-static unsigned long gma_write_acpi_tables(const struct device *const dev,
- unsigned long current,
- struct acpi_rsdp *const rsdp)
-{
- igd_opregion_t *opregion = (igd_opregion_t *)current;
- global_nvs_t *gnvs;
-
- if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
- return current;
-
- current += sizeof(igd_opregion_t);
-
- /* GNVS has been already set up */
- gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
- if (gnvs) {
- /* IGD OpRegion Base Address */
- gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
- } else {
- printk(BIOS_ERR, "Error: GNVS table not found.\n");
- }
-
- current = acpi_align_current(current);
- return current;
-}
-
static struct pci_operations gma_pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};
@@ -555,7 +516,6 @@ static struct device_operations gma_func0_ops = {
.init = gma_func0_init,
.acpi_fill_ssdt = gma_generate_ssdt,
.ops_pci = &gma_pci_ops,
- .write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short pci_device_ids[] = {
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index dfdd2fa34e..181aee56e7 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -18,8 +18,6 @@
#include <pc80/vga.h>
#include <pc80/vga_io.h>
#include <commonlib/helpers.h>
-#include <cbmem.h>
-#include <southbridge/intel/i82801gx/nvs.h>
#include <types.h>
#include "i945.h"
@@ -43,19 +41,6 @@
#define DEFAULT_BLC_PWM 180
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
- const global_nvs_t *gnvs_ptr = gnvs;
- return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
- global_nvs_t *gnvs_ptr = gnvs;
- if (gnvs_ptr)
- gnvs_ptr->aslb = aslb;
-}
-
static int gtt_setup(u8 *mmiobase)
{
unsigned long PGETBL_save;
@@ -677,6 +662,8 @@ static void gma_func0_init(struct device *dev)
{
u32 reg32;
+ intel_gma_init_igd_opregion();
+
/* Unconditionally reset graphics */
pci_write_config8(dev, GDRST, 1);
udelay(50);
@@ -707,8 +694,6 @@ static void gma_func0_init(struct device *dev)
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
}
-
- intel_gma_restore_opregion();
}
/* This doesn't reclaim stolen UMA memory, but IGD could still
@@ -763,32 +748,6 @@ static void gma_func0_read_resources(struct device *dev)
pci_dev_read_resources(dev);
}
-static unsigned long
-gma_write_acpi_tables(const struct device *const dev,
- unsigned long current,
- struct acpi_rsdp *const rsdp)
-{
- igd_opregion_t *opregion = (igd_opregion_t *)current;
- global_nvs_t *gnvs;
-
- if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
- return current;
-
- current += sizeof(igd_opregion_t);
-
- /* GNVS has been already set up */
- gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
- if (gnvs) {
- /* IGD OpRegion Base Address */
- gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
- } else {
- printk(BIOS_ERR, "Error: GNVS table not found.\n");
- }
-
- current = acpi_align_current(current);
- return current;
-}
-
static const char *gma_acpi_name(const struct device *dev)
{
return "GFX0";
@@ -807,7 +766,6 @@ static struct device_operations gma_func0_ops = {
.disable = gma_func0_disable,
.ops_pci = &gma_pci_ops,
.acpi_name = gma_acpi_name,
- .write_acpi_tables = gma_write_acpi_tables,
};
diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c
index 1836d84253..6de64fb065 100644
--- a/src/northbridge/intel/ironlake/gma.c
+++ b/src/northbridge/intel/ironlake/gma.c
@@ -13,9 +13,7 @@
#include <drivers/intel/gma/intel_bios.h>
#include <drivers/intel/gma/libgfxinit.h>
#include <pc80/vga.h>
-#include <southbridge/intel/ibexpeak/nvs.h>
#include <drivers/intel/gma/opregion.h>
-#include <cbmem.h>
#include <types.h>
#include "chip.h"
@@ -64,19 +62,6 @@ int gtt_poll(u32 reg, u32 mask, u32 value)
return 0;
}
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
- const global_nvs_t *gnvs_ptr = gnvs;
- return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
- global_nvs_t *gnvs_ptr = gnvs;
- if (gnvs_ptr)
- gnvs_ptr->aslb = aslb;
-}
-
static void gma_pm_init_post_vbios(struct device *dev)
{
struct northbridge_intel_ironlake_config *conf = dev->chip_info;
@@ -152,6 +137,8 @@ static void gma_func0_init(struct device *dev)
{
u32 reg32;
+ intel_gma_init_igd_opregion();
+
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
@@ -180,7 +167,6 @@ static void gma_func0_init(struct device *dev)
gma_pm_init_post_vbios(dev);
gma_enable_swsci();
- intel_gma_restore_opregion();
}
static void gma_read_resources(struct device *dev)
@@ -209,32 +195,6 @@ static void gma_generate_ssdt(const struct device *device)
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
-static unsigned long
-gma_write_acpi_tables(const struct device *const dev,
- unsigned long current,
- struct acpi_rsdp *const rsdp)
-{
- igd_opregion_t *opregion = (igd_opregion_t *)current;
- global_nvs_t *gnvs;
-
- if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
- return current;
-
- current += sizeof(igd_opregion_t);
-
- /* GNVS has been already set up */
- gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
- if (gnvs) {
- /* IGD OpRegion Base Address */
- gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
- } else {
- printk(BIOS_ERR, "Error: GNVS table not found.\n");
- }
-
- current = acpi_align_current(current);
- return current;
-}
-
static struct pci_operations gma_pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};
@@ -246,7 +206,6 @@ static struct device_operations gma_func0_ops = {
.acpi_fill_ssdt = gma_generate_ssdt,
.init = gma_func0_init,
.ops_pci = &gma_pci_ops,
- .write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short pci_device_ids[] = {
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index b0ecfe1d64..e2d0d18bad 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -12,8 +12,6 @@
#include <drivers/intel/gma/intel_bios.h>
#include <drivers/intel/gma/i915.h>
#include <drivers/intel/gma/opregion.h>
-#include <southbridge/intel/i82801gx/nvs.h>
-#include <cbmem.h>
#include <pc80/vga.h>
#include <pc80/vga_io.h>
#include <types.h>
@@ -42,19 +40,6 @@
static struct resource *gtt_res = NULL;
static struct resource *mmio_res = NULL;
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
- const global_nvs_t *gnvs_ptr = gnvs;
- return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
- global_nvs_t *gnvs_ptr = gnvs;
- if (gnvs_ptr)
- gnvs_ptr->aslb = aslb;
-}
-
static int gtt_setup(u8 *mmiobase)
{
u32 gttbase;
@@ -235,6 +220,8 @@ static void gma_func0_init(struct device *dev)
{
u32 reg32;
+ intel_gma_init_igd_opregion();
+
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
@@ -273,33 +260,6 @@ static void gma_func0_init(struct device *dev)
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT PINEVIEW");
}
-
- intel_gma_restore_opregion();
-}
-
-static unsigned long gma_write_acpi_tables(const struct device *const dev,
- unsigned long current,
- struct acpi_rsdp *const rsdp)
-{
- igd_opregion_t *opregion = (igd_opregion_t *)current;
- global_nvs_t *gnvs;
-
- if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
- return current;
-
- current += sizeof(igd_opregion_t);
-
- /* GNVS has been already set up */
- gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
- if (gnvs) {
- /* IGD OpRegion Base Address */
- gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
- } else {
- printk(BIOS_ERR, "Error: GNVS table not found.\n");
- }
-
- current = acpi_align_current(current);
- return current;
}
static const char *gma_acpi_name(const struct device *dev)
@@ -318,7 +278,6 @@ static struct device_operations gma_func0_ops = {
.init = gma_func0_init,
.ops_pci = &gma_pci_ops,
.acpi_name = gma_acpi_name,
- .write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short pci_device_ids[] =
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 9ff68d1e7d..82e43fc575 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -10,10 +10,8 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <drivers/intel/gma/libgfxinit.h>
-#include <southbridge/intel/bd82x6x/nvs.h>
#include <drivers/intel/gma/opregion.h>
#include <southbridge/intel/bd82x6x/pch.h>
-#include <cbmem.h>
#include <types.h>
#include "chip.h"
@@ -302,19 +300,6 @@ int gtt_poll(u32 reg, u32 mask, u32 value)
return 0;
}
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
- const global_nvs_t *gnvs_ptr = gnvs;
- return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
- global_nvs_t *gnvs_ptr = gnvs;
- if (gnvs_ptr)
- gnvs_ptr->aslb = aslb;
-}
-
static void gma_pm_init_pre_vbios(struct device *dev)
{
u32 reg32;
@@ -602,6 +587,8 @@ static void gma_func0_init(struct device *dev)
{
u32 reg32;
+ intel_gma_init_igd_opregion();
+
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
@@ -636,7 +623,6 @@ static void gma_func0_init(struct device *dev)
}
gma_enable_swsci();
- intel_gma_restore_opregion();
}
static void gma_generate_ssdt(const struct device *device)
@@ -646,31 +632,6 @@ static void gma_generate_ssdt(const struct device *device)
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
-static unsigned long gma_write_acpi_tables(const struct device *const dev,
- unsigned long current,
- struct acpi_rsdp *const rsdp)
-{
- igd_opregion_t *opregion = (igd_opregion_t *)current;
- global_nvs_t *gnvs;
-
- if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
- return current;
-
- current += sizeof(igd_opregion_t);
-
- /* GNVS has been already set up */
- gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
- if (gnvs) {
- /* IGD OpRegion Base Address */
- gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
- } else {
- printk(BIOS_ERR, "Error: GNVS table not found.\n");
- }
-
- current = acpi_align_current(current);
- return current;
-}
-
static const char *gma_acpi_name(const struct device *dev)
{
return "GFX0";
@@ -702,7 +663,6 @@ static struct device_operations gma_func0_ops = {
.disable = gma_func0_disable,
.ops_pci = &gma_pci_ops,
.acpi_name = gma_acpi_name,
- .write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short pci_device_ids[] = {
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index 0067d71bbc..004960fd8c 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -6,7 +6,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <commonlib/helpers.h>
-#include <cbmem.h>
#include <drivers/intel/gma/intel_bios.h>
#include <drivers/intel/gma/edid.h>
#include <drivers/intel/gma/i915.h>
@@ -19,31 +18,14 @@
#include "drivers/intel/gma/i915_reg.h"
#include "x4x.h"
-#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
-#include <southbridge/intel/i82801jx/nvs.h>
-#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
-#include <southbridge/intel/i82801gx/nvs.h>
-#endif
-
#define BASE_FREQUENCY 96000
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
- const global_nvs_t *gnvs_ptr = gnvs;
- return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
- global_nvs_t *gnvs_ptr = gnvs;
- if (gnvs_ptr)
- gnvs_ptr->aslb = aslb;
-}
-
static void gma_func0_init(struct device *dev)
{
u32 reg32;
+ intel_gma_init_igd_opregion();
+
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
@@ -65,8 +47,6 @@ static void gma_func0_init(struct device *dev)
} else {
pci_dev_init(dev);
}
-
- intel_gma_restore_opregion();
}
static void gma_func0_disable(struct device *dev)
@@ -86,32 +66,6 @@ static void gma_generate_ssdt(const struct device *device)
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
-static unsigned long
-gma_write_acpi_tables(const struct device *const dev,
- unsigned long current,
- struct acpi_rsdp *const rsdp)
-{
- igd_opregion_t *opregion = (igd_opregion_t *)current;
- global_nvs_t *gnvs;
-
- if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
- return current;
-
- current += sizeof(igd_opregion_t);
-
- /* GNVS has been already set up */
- gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
- if (gnvs) {
- /* IGD OpRegion Base Address */
- gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
- } else {
- printk(BIOS_ERR, "Error: GNVS table not found.\n");
- }
-
- current = acpi_align_current(current);
- return current;
-}
-
static const char *gma_acpi_name(const struct device *dev)
{
return "GFX0";
@@ -130,7 +84,6 @@ static struct device_operations gma_func0_ops = {
.ops_pci = &gma_pci_ops,
.disable = gma_func0_disable,
.acpi_name = gma_acpi_name,
- .write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short pci_device_ids[] = {
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-08 00:28:06 +0000