diff options
Diffstat (limited to 'src/northbridge')
22 files changed, 307 insertions, 238 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a25a8df4e8..253a209965 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -137,7 +137,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, +static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { // I want to put sb chain in bus 0 can I? @@ -149,7 +149,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_bus; u32 min_bus; - u32 is_sublink1 = (link>3); + u32 is_sublink1 = (link_num>3); device_t devx; u32 busses; u32 segn = max>>8; @@ -162,7 +162,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, if(is_sublink1) { u32 regpos; u32 reg; - regpos = 0x170 + 4 * (link&3); // it is only on sublink0 + regpos = 0x170 + 4 * (link_num&3); // it is only on sublink0 reg = pci_read_config32(dev, regpos); if(reg & 1) return max; // already ganged no sblink1 devx = get_node_pci(nodeid, 4); @@ -171,15 +171,15 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, devx = dev; - dev->link[link].cap = 0x80 + ((link&3) *0x20); + link->cap = 0x80 + ((link_num&3) *0x20); do { - link_type = pci_read_config32(devx, dev->link[link].cap + 0x18); + link_type = pci_read_config32(devx, link->cap + 0x18); } while(link_type & ConnectionPending); if (!(link_type & LinkConnected)) { return max; } do { - link_type = pci_read_config32(devx, dev->link[link].cap + 0x18); + link_type = pci_read_config32(devx, link->cap + 0x18); } while(!(link_type & InitComplete)); if (!(link_type & NonCoherent)) { return max; @@ -187,7 +187,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, /* See if there is an available configuration space mapping * register in function 1. */ - ht_c_index = get_ht_c_index(nodeid, link, &sysconf); + ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf); #if CONFIG_EXT_CONF_SUPPORT == 0 if(ht_c_index>=4) return max; @@ -199,7 +199,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, */ #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 - if((nodeid == 0) && (sblink==link)) { // actually max is 0 here + if((nodeid == 0) && (sblink==link_num)) { // actually max is 0 here min_bus = max; } #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -221,26 +221,26 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, #endif max_bus = 0xfc | (segn<<8); - dev->link[link].secondary = min_bus; - dev->link[link].subordinate = max_bus; + link->secondary = min_bus; + link->subordinate = max_bus; /* Read the existing primary/secondary/subordinate bus * number configuration. */ - busses = pci_read_config32(devx, dev->link[link].cap + 0x14); + busses = pci_read_config32(devx, link->cap + 0x14); /* Configure the bus numbers for this bridge: the configuration * transactions will not be propagates by the bridge if it is * not correctly configured */ busses &= 0xffff00ff; - busses |= ((u32)(dev->link[link].secondary) << 8); - pci_write_config32(devx, dev->link[link].cap + 0x14, busses); + busses |= ((u32)(link->secondary) << 8); + pci_write_config32(devx, link->cap + 0x14, busses); /* set the config map space */ - set_config_map_reg(nodeid, link, ht_c_index, dev->link[link].secondary, dev->link[link].subordinate, sysconf.segbit, sysconf.nodes); + set_config_map_reg(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link @@ -255,17 +255,17 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid); + max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ if(ht_c_index>3) { // clear the extend reg - clear_config_map_reg(nodeid, link, ht_c_index, (max+1)>>sysconf.segbit, (dev->link[link].subordinate)>>sysconf.segbit, sysconf.nodes); + clear_config_map_reg(nodeid, link_num, ht_c_index, (max+1)>>sysconf.segbit, (link->subordinate)>>sysconf.segbit, sysconf.nodes); } - dev->link[link].subordinate = max; - set_config_map_reg(nodeid, link, ht_c_index, dev->link[link].secondary, dev->link[link].subordinate, sysconf.segbit, sysconf.nodes); + link->subordinate = max; + set_config_map_reg(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); sysconf.ht_c_num++; { @@ -278,14 +278,14 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, sysconf.hcdn_reg[ht_c_index] = temp; } - store_ht_c_conf_bus(nodeid, link, ht_c_index, dev->link[link].secondary, dev->link[link].subordinate, &sysconf); + store_ht_c_conf_bus(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); return max; } -static u32 amdfam10_scan_chains(device_t dev, u32 max) +static unsigned amdfam10_scan_chains(device_t dev, unsigned max) { unsigned nodeid; - u32 link; + struct bus *link; unsigned sblink = sysconf.sblk; unsigned offset_unitid = 0; @@ -297,7 +297,9 @@ static u32 amdfam10_scan_chains(device_t dev, u32 max) #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif - max = amdfam10_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 + for (link = dev->link_list; link; link = link->next) + if (link->link_num == sblink) + max = amdfam10_scan_chain(dev, nodeid, link, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 } #endif @@ -305,19 +307,19 @@ static u32 amdfam10_scan_chains(device_t dev, u32 max) max = check_segn(dev, max, sysconf.nodes, &sysconf); #endif - for(link = 0; link < dev->links; link++) { + for(link = dev->link_list; link; link = link->next) { #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - if( (nodeid == 0) && (sblink == link) ) continue; //already done + if( (nodeid == 0) && (sblink == link->link_num) ) continue; //already done #endif offset_unitid = 0; #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - if((nodeid == 0) && (sblink == link)) + if((nodeid == 0) && (sblink == link->link_num)) #endif offset_unitid = 1; #endif - max = amdfam10_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); + max = amdfam10_scan_chain(dev, nodeid, link, link->link_num, sblink, max, offset_unitid); } return max; } @@ -482,12 +484,12 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) static void amdfam10_read_resources(device_t dev) { - u32 nodeid, link; - + u32 nodeid; + struct bus *link; nodeid = amdfam10_nodeid(dev); - for(link = 0; link < dev->links; link++) { - if (dev->link[link].children) { - amdfam10_link_read_bases(dev, nodeid, link); + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam10_link_read_bases(dev, nodeid, link->link_num); } } } @@ -496,7 +498,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; - unsigned reg, link; + unsigned reg, link_num; char buf[50]; /* Make certain the resource has actually been set */ @@ -525,20 +527,20 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, /* Get the register and link */ reg = resource->index & 0xfff; // 4k - link = IOINDEX_LINK(resource->index); + link_num = IOINDEX_LINK(resource->index); if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link, reg, rbase>>8, rend>>8); - store_conf_io_addr(nodeid, link, reg, (resource->index >> 24), rbase>>8, rend>>8); + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] - store_conf_mmio_addr(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8); + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] + store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %02x link %02x>", - nodeid, link); + sprintf(buf, " <node %x link %x>", + nodeid, link_num); report_resource_stored(dev, resource, buf); } @@ -553,18 +555,18 @@ extern device_t vga_pri; // the primary vga device, defined in device.c static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) { - unsigned link; + struct bus *link; /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ - for (link = 0; link < dev->links; link++) { - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_CONSOLE_VGA_MULTI == 1 - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, - dev->link[link].secondary,dev->link[link].subordinate); + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if((vga_pri->bus->secondary >= dev->link[link].secondary ) && - (vga_pri->bus->secondary <= dev->link[link].subordinate ) + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) ) #endif break; @@ -572,16 +574,17 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) } /* no VGA card installed */ - if (link == dev->links) + if (link == NULL) return; - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link); - set_vga_enable_reg(nodeid, link); + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); + set_vga_enable_reg(nodeid, link->link_num); } static void amdfam10_set_resources(device_t dev) { - u32 nodeid, link; + unsigned nodeid; + struct bus *bus; struct resource *res; /* Find the nodeid */ @@ -594,9 +597,7 @@ static void amdfam10_set_resources(device_t dev) amdfam10_set_resource(dev, res, nodeid); } - for(link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; + for(bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { assign_resources(bus); } @@ -672,22 +673,22 @@ static void amdfam10_domain_read_resources(device_t dev) #if CONFIG_PCI_64BIT_PREF_MEM == 0 pci_domain_read_resources(dev); #else - unsigned link; + struct bus *link; struct resource *resource; - for(link=0; link<dev->links; link++) { + for(link=dev->link_list; link; link = link->next) { /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link<<2)); + resource = new_resource(dev, 0|(link->link_num<<2)); resource->base = 0x400; resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO; /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link<<2)); + resource = new_resource(dev, 1|(link->link_num<<2)); resource->limit = 0xfcffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link<<2)); + resource = new_resource(dev, 2|(link->link_num<<2)); resource->limit = 0xfcffffffffULL; resource->flags = IORESOURCE_MEM; } @@ -881,7 +882,7 @@ static void amdfam10_domain_set_resources(device_t dev) unsigned long mmio_basek; u32 pci_tolm; int i, idx; - u32 link; + struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; u32 reset_memhole = 1; @@ -889,12 +890,12 @@ static void amdfam10_domain_set_resources(device_t dev) #if CONFIG_PCI_64BIT_PREF_MEM == 1 - for(link = 0; link < dev->links; link++) { + for(link = dev->link_list; link; link = link->next) { /* Now reallocate the pci resources memory with the * highest addresses I can manage. */ - mem1 = find_resource(dev, 1|(link<<2)); - mem2 = find_resource(dev, 2|(link<<2)); + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", mem1->base, mem1->limit, mem1->size, mem1->align); @@ -939,8 +940,8 @@ static void amdfam10_domain_set_resources(device_t dev) #endif pci_tolm = 0xffffffffUL; - for(link = 0; link<dev->links; link++) { - pci_tolm = find_pci_tolm(&dev->link[link], pci_tolm); + for(link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link, pci_tolm); } // FIXME handle interleaved nodes. If you fix this here, please fix @@ -1084,11 +1085,9 @@ static void amdfam10_domain_set_resources(device_t dev) #endif } - for(link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; - if (bus->children) { - assign_resources(bus); + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); } } } @@ -1097,6 +1096,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) { u32 reg; int i; + struct bus *link; /* Unmap all of the HT chains */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); @@ -1114,8 +1114,8 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) #endif - for(i = 0; i < dev->links; i++) { - max = pci_scan_bus(&dev->link[i], PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); + for(link = dev->link_list; link; link = link->next) { + max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); } /* Tune the hypertransport transaction for best performance. @@ -1129,12 +1129,12 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) u32 httc; httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); httc &= ~HTTC_RSP_PASS_PW; - if (!dev->link[0].disable_relaxed_ordering) { + if (!dev->link_list->disable_relaxed_ordering) { httc |= HTTC_RSP_PASS_PW; } printk(BIOS_SPEW, "%s passpw: %s\n", dev_path(dev), - (!dev->link[0].disable_relaxed_ordering)? + (!dev->link_list->disable_relaxed_ordering)? "enabled":"disabled"); pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } @@ -1197,6 +1197,42 @@ static void sysconf_init(device_t dev) // first node #endif } +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1250,7 +1286,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); pci_domain = dev_mc->bus->dev; if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { - if((pci_domain->links==1) && (pci_domain->link[0].children == dev_mc)) { + if((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); @@ -1279,18 +1315,19 @@ static u32 cpu_bus_scan(device_t dev, u32 max) #if CONFIG_CBB && (NODE_NUMS > 32) if(nodes>32) { // need to put node 32 to node 63 to bus 0xfe - if(pci_domain->links==1) { - pci_domain->links++; // from 1 to 2 - pci_domain->link[1].link = 1; - pci_domain->link[1].dev = pci_domain; - pci_domain->link[1].children = 0; - printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(pci_domain), pci_domain->links); + if(pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); } - pci_domain->link[1].secondary = CONFIG_CBB - 1; + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; } #endif /* Find which cpus are present */ - cpu_bus = &dev->link[0]; + cpu_bus = dev->link_list; for(i = 0; i < nodes; i++) { device_t cdb_dev, cpu; struct device_path cpu_path; @@ -1304,7 +1341,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if(i>=32) { busn--; devn-=32; - pbus = &(pci_domain->link[1]); + pbus = pci_domain->link_list->next); } #endif @@ -1325,21 +1362,13 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Ok, We need to set the links for that device. * otherwise the device under it will not be scanned */ - int link; int linknum; #if CONFIG_HT3_SUPPORT==1 linknum = 8; #else linknum = 4; #endif - if (cdb_dev->links < linknum) { - for(link=cdb_dev->links; link<linknum; link++) { - cdb_dev->link[link].link = link; - cdb_dev->link[link].dev = cdb_dev; - } - cdb_dev->links = linknum; - printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(cdb_dev), cdb_dev->links); - } + add_more_links(cdb_dev, linknum); } cores_found = 0; // one core @@ -1410,7 +1439,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index b798b0bf42..227a02edf0 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -81,7 +81,7 @@ static u32 amdk8_nodeid(device_t dev) return (dev->path.pci.devfn >> 3) - 0x18; } -static u32 amdk8_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, +static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { @@ -94,15 +94,15 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, u32 min_bus; u32 max_devfn; - dev->link[link].cap = 0x80 + (link *0x20); + link->cap = 0x80 + (link_num *0x20); do { - link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); + link_type = pci_read_config32(dev, link->cap + 0x18); } while(link_type & ConnectionPending); if (!(link_type & LinkConnected)) { return max; } do { - link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); + link_type = pci_read_config32(dev, link->cap + 0x18); } while(!(link_type & InitComplete)); if (!(link_type & NonCoherent)) { return max; @@ -120,7 +120,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, } if (((config & 3) == 3) && (((config >> 4) & 7) == nodeid) && - (((config >> 8) & 3) == link)) { + (((config >> 8) & 3) == link_num)) { break; } } @@ -140,7 +140,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, */ #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 - if((nodeid == 0) && (sblink==link)) { // actually max is 0 here + if((nodeid == 0) && (sblink==link_num)) { // actually max is 0 here min_bus = max; } #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -160,13 +160,13 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, #endif max_bus = 0xff; - dev->link[link].secondary = min_bus; - dev->link[link].subordinate = max_bus; + link->secondary = min_bus; + link->subordinate = max_bus; /* Read the existing primary/secondary/subordinate bus * number configuration. */ - busses = pci_read_config32(dev, dev->link[link].cap + 0x14); + busses = pci_read_config32(dev, link->cap + 0x14); config_busses = f1_read_config32(config_reg); /* Configure the bus numbers for this bridge: the configuration @@ -175,17 +175,17 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, */ busses &= 0xff000000; busses |= (((unsigned int)(dev->bus->secondary) << 0) | - ((unsigned int)(dev->link[link].secondary) << 8) | - ((unsigned int)(dev->link[link].subordinate) << 16)); - pci_write_config32(dev, dev->link[link].cap + 0x14, busses); + ((unsigned int)(link->secondary) << 8) | + ((unsigned int)(link->subordinate) << 16)); + pci_write_config32(dev, link->cap + 0x14, busses); config_busses &= 0x000fc88; config_busses |= (3 << 0) | /* rw enable, no device compare */ (( nodeid & 7) << 4) | - (( link & 3 ) << 8) | - ((dev->link[link].secondary) << 16) | - ((dev->link[link].subordinate) << 24); + (( link_num & 3 ) << 8) | + ((link->secondary) << 16) | + ((link->subordinate) << 24); f1_write_config32(config_reg, config_busses); /* Now we can scan all of the subordinate busses i.e. the @@ -200,18 +200,18 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid); + max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - dev->link[link].subordinate = max; + link->subordinate = max; busses = (busses & 0xff00ffff) | - ((unsigned int) (dev->link[link].subordinate) << 16); - pci_write_config32(dev, dev->link[link].cap + 0x14, busses); + ((unsigned int) (link->subordinate) << 16); + pci_write_config32(dev, link->cap + 0x14, busses); config_busses = (config_busses & 0x00ffffff) | - (dev->link[link].subordinate << 24); + (link->subordinate << 24); f1_write_config32(config_reg, config_busses); { @@ -232,7 +232,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, static unsigned amdk8_scan_chains(device_t dev, unsigned max) { unsigned nodeid; - unsigned link; + struct bus *link; unsigned sblink = 0; unsigned offset_unitid = 0; @@ -244,23 +244,25 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif - max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 + for (link = dev->link_list; link; link = link->next) + if (link->link_num == sblink) + max = amdk8_scan_chain(dev, nodeid, link, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 #endif } - for (link = 0; link < dev->links; link++) { + for (link = dev->link_list; link; link = link->next) { #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - if( (nodeid == 0) && (sblink == link) ) continue; //already done + if( (nodeid == 0) && (sblink == link->link_num) ) continue; //already done #endif offset_unitid = 0; #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - if((nodeid == 0) && (sblink == link)) + if((nodeid == 0) && (sblink == link->link_num)) #endif offset_unitid = 1; #endif - max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); + max = amdk8_scan_chain(dev, nodeid, link, link->link_num, sblink, max, offset_unitid); } return max; } @@ -375,21 +377,22 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid); static void amdk8_read_resources(device_t dev) { - unsigned nodeid, link; + unsigned nodeid; + struct bus *link; nodeid = amdk8_nodeid(dev); - for(link = 0; link < dev->links; link++) { - if (dev->link[link].children) { - amdk8_link_read_bases(dev, nodeid, link); + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + amdk8_link_read_bases(dev, nodeid, link->link_num); } } - amdk8_create_vga_resource(dev, nodeid); } static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid) { + struct bus *link; resource_t rbase, rend; - unsigned reg, link; + unsigned reg, link_num; char buf[50]; /* Make certain the resource has actually been set */ @@ -426,7 +429,17 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned /* Get the register and link */ reg = resource->index & 0xfc; - link = IOINDEX_LINK(resource->index); + link_num = IOINDEX_LINK(resource->index); + + for (link = dev->link_list; link; link = link->next) + if (link->link_num == link_num) + break; + + if (link == NULL) { + printk(BIOS_ERR, "%s: can't find link %x for %lx\n", __func__, + link_num, resource->index); + return; + } if (resource->flags & IORESOURCE_IO) { u32 base, limit; @@ -437,15 +450,15 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned base |= 3; limit &= 0xfe000fc8; limit |= rend & 0x01fff000; - limit |= (link & 3) << 4; + limit |= (link_num & 3) << 4; limit |= (nodeid & 7); - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link 0x%x\n", - __func__, dev_path(dev), link); + __func__, dev_path(dev), link_num); base |= PCI_IO_BASE_VGA_EN; } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { base |= PCI_IO_BASE_NO_ISA; } @@ -461,14 +474,14 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned base |= 3; limit &= 0x00000048; limit |= (rend >> 8) & 0xffffff00; - limit |= (link & 3) << 4; + limit |= (link_num & 3) << 4; limit |= (nodeid & 7); f1_write_config32(reg + 0x4, limit); f1_write_config32(reg, base); } resource->flags |= IORESOURCE_STORED; sprintf(buf, " <node %x link %x>", - nodeid, link); + nodeid, link_num); report_resource_stored(dev, resource, buf); } @@ -479,18 +492,18 @@ extern device_t vga_pri; // the primary vga device, defined in device.c static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) { struct resource *resource; - unsigned link; + struct bus *link; /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ - for (link = 0; link < dev->links; link++) { - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_CONSOLE_VGA_MULTI == 1 - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, - dev->link[link].secondary,dev->link[link].subordinate); + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if((vga_pri->bus->secondary >= dev->link[link].secondary ) && - (vga_pri->bus->secondary <= dev->link[link].subordinate ) + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) ) #endif break; @@ -498,13 +511,13 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) } /* no VGA card installed */ - if (link == dev->links) + if (link == NULL) return; - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link); + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); /* allocate a temp resource for the legacy VGA buffer */ - resource = new_resource(dev, IOINDEX(4, link)); + resource = new_resource(dev, IOINDEX(4, link->link_num)); if(!resource){ printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev)); return; @@ -518,7 +531,8 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) static void amdk8_set_resources(device_t dev) { - unsigned nodeid, link; + unsigned nodeid; + struct bus *bus; struct resource *res; /* Find the nodeid */ @@ -553,9 +567,7 @@ static void amdk8_set_resources(device_t dev) compact_resources(dev); - for(link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; + for(bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { assign_resources(bus); } @@ -909,7 +921,7 @@ static void amdk8_domain_set_resources(device_t dev) } #endif - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); // FIXME handle interleaved nodes. If you fix this here, please fix // amdfam10, too. @@ -1066,7 +1078,7 @@ static void amdk8_domain_set_resources(device_t dev) } #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } @@ -1078,7 +1090,7 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max); + max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); /* Tune the hypertransport transaction for best performance. * Including enabling relaxed ordering if it is safe. @@ -1091,12 +1103,12 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) u32 httc; httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); httc &= ~HTTC_RSP_PASS_PW; - if (!dev->link[0].disable_relaxed_ordering) { + if (!dev->link_list->disable_relaxed_ordering) { httc |= HTTC_RSP_PASS_PW; } printk(BIOS_SPEW, "%s passpw: %s\n", dev_path(dev), - (!dev->link[0].disable_relaxed_ordering)? + (!dev->link_list->disable_relaxed_ordering)? "enabled":"disabled"); pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } @@ -1113,6 +1125,42 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = &pci_cf8_conf1, }; +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1165,7 +1213,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } /* Find which cpus are present */ - cpu_bus = &dev->link[0]; + cpu_bus = dev->link_list; for(i = 0; i < sysconf.nodes; i++) { device_t cpu_dev, cpu; struct device_path cpu_path; @@ -1187,11 +1235,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) */ dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0)); if(dev_f0) { - dev_f0->links = 3; - for(local_j=0;local_j<3;local_j++) { - dev_f0->link[local_j].link = local_j; - dev_f0->link[local_j].dev = dev_f0; - } + add_more_links(dev_f0, 3); } } @@ -1290,7 +1334,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index 1176744c87..8b60345b0d 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -115,8 +115,8 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned int tomk, tolmk; unsigned int ramreg = 0; @@ -163,7 +163,7 @@ static void pci_domain_set_resources(device_t dev) idx = 10; ram_resource(dev, idx++, 0, tolmk); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -177,7 +177,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__); - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index bb41fd057d..4846ac328f 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -303,11 +303,9 @@ static void set_resources(struct device *dev) pci_set_resource(dev, resource); } #endif - unsigned link; + struct bus *bus; - for(link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; + for(bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { assign_resources(bus); } @@ -402,8 +400,8 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; u32 pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned int tomk, tolmk; unsigned int ramreg = 0; @@ -444,7 +442,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, tolmk); } #endif - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -457,7 +455,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 8fd8d9ecd2..5202de21e8 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -318,7 +318,6 @@ static void northbridge_init(device_t dev) static void northbridge_set_resources(struct device *dev) { - unsigned link; uint8_t line; #if 0 @@ -331,9 +330,8 @@ static void northbridge_set_resources(struct device *dev) } #endif - for (link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; + struct bus *bus; + for (bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n", bus->secondary); @@ -402,7 +400,7 @@ static void pci_domain_set_resources(device_t dev) printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); - mc_dev = dev->link[0].children; + mc_dev = dev->link_list->children; if (mc_dev) { tomk = get_systop() / 1024; /* Report the memory regions @@ -418,7 +416,7 @@ static void pci_domain_set_resources(device_t dev) #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static void pci_domain_enable(device_t dev) @@ -452,7 +450,7 @@ static void cpu_bus_init(device_t dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index a2e4b245ee..5db56dc482 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -58,8 +58,8 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. * This is all computed in kilobytes and converted to/from @@ -135,7 +135,7 @@ static void pci_domain_set_resources(device_t dev) high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -149,7 +149,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 02f7c45495..c0580bbe3e 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -62,7 +62,7 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); #if 1 printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); @@ -72,7 +72,7 @@ static void pci_domain_set_resources(device_t dev) pci_tolm = 0xe0000000; /* Ensure pci_tolm is 128M aligned */ pci_tolm &= 0xf8000000; - mc_dev = dev->link[0].children; + mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. * This is all computed in kilobytes and converted to/from @@ -151,7 +151,7 @@ static void pci_domain_set_resources(device_t dev) high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static u32 e7520_domain_scan_bus(device_t dev, u32 max) @@ -219,7 +219,7 @@ static const struct pci_driver mc_driver __pci_driver = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index a227f22987..2af6c25ae8 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -62,7 +62,7 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); #if 1 printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); @@ -72,7 +72,7 @@ static void pci_domain_set_resources(device_t dev) pci_tolm = 0xe0000000; /* Ensure pci_tolm is 128M aligned */ pci_tolm &= 0xf8000000; - mc_dev = dev->link[0].children; + mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. * This is all computed in kilobytes and converted to/from @@ -151,7 +151,7 @@ static void pci_domain_set_resources(device_t dev) high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static u32 e7525_domain_scan_bus(device_t dev, u32 max) @@ -219,7 +219,7 @@ static const struct pci_driver mc_driver __pci_driver = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 0675aea6bc..482e6006a5 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -83,7 +83,7 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; u32 pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); #if 1 printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); @@ -93,7 +93,7 @@ static void pci_domain_set_resources(device_t dev) pci_tolm = 0xe0000000; /* Ensure pci_tolm is 128M aligned */ pci_tolm &= 0xf8000000; - mc_dev = dev->link[0].children; + mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. * This is all computed in kilobytes and converted to/from @@ -172,7 +172,7 @@ static void pci_domain_set_resources(device_t dev) high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static u32 i3100_domain_scan_bus(device_t dev, u32 max) @@ -240,7 +240,7 @@ static const struct pci_driver mc_driver __pci_driver = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index 42f624aaf7..a17cb0b3f2 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -56,7 +56,7 @@ static void pcie_init(struct device *dev) static void pcie_bus_enable_resources(struct device *dev) { - if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n"); pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8); diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 772ab1c8f3..c5f09344bc 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -82,8 +82,8 @@ static void i440bx_domain_set_resources(device_t dev) device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; int idx; @@ -118,7 +118,7 @@ static void i440bx_domain_set_resources(device_t dev) high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -131,7 +131,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index 7ebc002c72..7c41e59c19 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -110,8 +110,8 @@ static void i440lx_domain_set_resources(device_t dev) device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; int idx; @@ -146,7 +146,7 @@ static void i440lx_domain_set_resources(device_t dev) high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -159,7 +159,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 5b68046e7e..612d6c0907 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -119,8 +119,8 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. @@ -178,7 +178,7 @@ static void pci_domain_set_resources(device_t dev) high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -191,7 +191,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index eb21b7cbb7..a1a389388d 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -111,8 +111,8 @@ static void pci_domain_set_resources(device_t dev) uint32_t pci_tolm; int igd_memory = 0; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (!mc_dev) return; @@ -152,7 +152,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 768, 256); ram_resource(dev, idx++, 1024, tolmk - 1024); - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ @@ -171,7 +171,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 3495fb6cfb..0438d09d93 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -83,8 +83,8 @@ static void pci_domain_set_resources(device_t dev) printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device); - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children->sibling; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children->sibling; printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor); printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device); @@ -134,7 +134,7 @@ static void pci_domain_set_resources(device_t dev) high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -147,7 +147,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 0812460cfe..81b61bda59 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -138,7 +138,7 @@ static void pci_domain_set_resources(device_t dev) /* Can we find out how much memory we can use at most * this way? */ - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm); printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n", @@ -208,7 +208,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ @@ -326,7 +326,7 @@ static const struct pci_driver mc_driver __pci_driver = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 3fbc358de5..2974d23da7 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -233,7 +233,7 @@ static void cn400_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Entering %s.\n", __func__); - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN400_MEMCTRL, 0); @@ -267,7 +267,7 @@ static void cn400_domain_set_resources(device_t dev) ram_resource(dev, idx++, 768, (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); printk(BIOS_SPEW, "Leaving %s.\n", __func__); } @@ -276,7 +276,7 @@ static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max) { printk(BIOS_DEBUG, "Entering %s.\n", __func__); - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max); return max; } @@ -290,7 +290,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 445ecf2780..b122a5e2fe 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -157,7 +157,7 @@ static void pci_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n"); - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0); @@ -199,7 +199,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 768, (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -212,7 +212,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index 6a69d434fb..3f5ed28120 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -87,7 +87,7 @@ static void pci_domain_set_resources(device_t dev) unsigned char rambits; int idx; - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0); rambits = pci_read_config8(mc_dev, 0x88); @@ -128,7 +128,7 @@ static void pci_domain_set_resources(device_t dev) /* TODO: Hole needed? Should this go elsewhere? */ ram_resource(dev, idx++, 0, 640); /* first 640k */ ram_resource(dev, idx++, 768, (tolmk - 768)); /* leave a hole for vga */ - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -141,7 +141,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 8fca0eae2c..1f15b7026e 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -98,8 +98,8 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; unsigned char rambits; @@ -140,7 +140,7 @@ static void pci_domain_set_resources(device_t dev) idx = 10; ram_resource(dev, idx++, 0, tolmk); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -153,7 +153,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 7ba9cd6316..d7fff335fe 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -158,8 +158,8 @@ static void pci_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n"); - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; unsigned char rambits; @@ -201,7 +201,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); /* first 640k */ ram_resource(dev, idx++, 768, tolmk - 768); /* leave a hole for vga */ } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -214,7 +214,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 37e559c026..ec978e878b 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -128,7 +128,7 @@ static void pci_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Entering vx800 pci_domain_set_resources.\n"); - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0); @@ -175,7 +175,7 @@ if register with invalid value we set frame buffer size to 32M for default, but /* Leave a hole for vga, 0xa0000 - 0xc0000 */ ram_resource(dev, idx++, 768, (tolmk - 768)); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -188,7 +188,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) |