summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdk8/raminit_test.c2
-rw-r--r--src/northbridge/intel/e7520/raminit.c66
-rw-r--r--src/northbridge/intel/e7520/raminit.h6
-rw-r--r--src/northbridge/via/vx800/examples/romstage.c10
4 files changed, 41 insertions, 43 deletions
diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c
index bfe1103207..329c1afb83 100644
--- a/src/northbridge/amd/amdk8/raminit_test.c
+++ b/src/northbridge/amd/amdk8/raminit_test.c
@@ -124,7 +124,7 @@ static void hlt(void)
{
longjmp(end_buf, 2);
}
-#include "../../../arch/i386/lib/console.c"
+#include "console/console.c"
unsigned long log2(unsigned long x)
{
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index bb4ebbdfe3..3965addcb2 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -67,7 +67,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
device_t dev;
unsigned where;
unsigned long reg;
- dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
+ dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + PCI_DEV(0, 0x00, 0);
where = register_values[i] & 0xff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+1];
@@ -181,27 +181,27 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
sz.side1 -= 29;
cum += (1 << sz.side1);
/* DRB = 0x60 */
- pci_write_config8(ctrl->f0, DRB + (i*2), cum);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum);
if( sz.side2 > 28) {
sz.side2 -= 29;
cum += (1 << sz.side2);
}
- pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum);
}
else {
- pci_write_config8(ctrl->f0, DRB + (i*2), cum);
- pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum);
}
}
/* set TOM top of memory 0xcc */
- pci_write_config16(ctrl->f0, TOM, cum);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), TOM, cum);
/* set TOLM top of low memory */
if(cum > 0x18) {
cum = 0x18;
}
cum <<= 11;
/* 0xc4 TOLM */
- pci_write_config16(ctrl->f0, TOLM, cum);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), TOLM, cum);
return 0;
}
@@ -279,7 +279,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
}
/* 0x70 DRA */
- pci_write_config32(ctrl->f0, DRA, dra);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra);
goto out;
val_err:
@@ -309,7 +309,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
static const int latency_indicies[] = { 26, 23, 9 };
/* 0x78 DRT */
- drt = pci_read_config32(ctrl->f0, DRT);
+ drt = pci_read_config32(PCI_DEV(0, 0x00, 0), DRT);
drt &= 3; /* save bits 1:0 */
for(first_dimm = 0; first_dimm < 4; first_dimm++) {
@@ -542,7 +542,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
}
/* 0x78 DRT */
- pci_write_config32(ctrl->f0, DRT, drt);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRT, drt);
return(cas_latency);
}
@@ -563,7 +563,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
static const unsigned char fsb_conversion[4] = {3,1,3,2};
/* 0x7c DRC */
- drc = pci_read_config32(ctrl->f0, DRC);
+ drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC);
for(cnt=0; cnt < 4; cnt++) {
if (!(dimm_mask & (1 << cnt))) {
continue;
@@ -727,12 +727,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
/* Set up northbridge values */
/* ODT enable */
- pci_write_config32(ctrl->f0, 0x88, 0xf0000180);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xf0000180);
/* Figure out which slots are Empty, Single, or Double sided */
for(i=0,t4=0,c2=0;i<8;i+=2) {
- c1 = pci_read_config8(ctrl->f0, DRB+i);
+ c1 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+i);
if(c1 == c2) continue;
- c2 = pci_read_config8(ctrl->f0, DRB+1+i);
+ c2 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+1+i);
if(c1 == c2)
t4 |= (1 << (i*4));
else
@@ -778,7 +778,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
print_debug_hex32(data32);
print_debug("\r\n");
- pci_write_config32(ctrl->f0, 0xb0, data32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0xb0, data32);
for(dimm=0;dimm<8;dimm+=1) {
@@ -1079,10 +1079,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
- pci_write_config32(ctrl->f0, DRM,
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRM,
0x00210000 | DIMM_MAP_LOGICAL);
#else
- pci_write_config32(ctrl->f0, DRM, 0x00211248);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00211248);
#endif
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
@@ -1097,20 +1097,20 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
cnt<4;cnt++) {
- pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0xa0+(cnt*4), iptr[cnt]);
}
/* 0x7c DRC */
- pci_write_config32(ctrl->f0, DRC, data32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);
/* turn the clocks on */
/* 0x8c CKDIS */
- pci_write_config16(ctrl->f0, CKDIS, 0x0000);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), CKDIS, 0x0000);
/* 0x9a DDRCSR Take subsystem out of idle */
- data16 = pci_read_config16(ctrl->f0, DDRCSR);
+ data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DDRCSR);
data16 &= ~(7 << 12);
data16 |= (3 << 12); /* use dual channel lock step */
- pci_write_config16(ctrl->f0, DDRCSR, data16);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), DDRCSR, data16);
/* program row size DRB */
spd_set_ram_size(ctrl, mask);
@@ -1287,23 +1287,23 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
set_on_dimm_termination_enable(ctrl);
}
else { /* ddr */
- pci_write_config32(ctrl->f0, 0x88, 0xa0000000 );
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xa0000000 );
}
/* receive enable calibration */
set_receive_enable(ctrl);
/* DQS */
- pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 );
for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
write32(cnt, dqs_data[i]);
}
- pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 );
/* Enable refresh */
/* 0x7c DRC */
data32 = drc & ~(3 << 20); /* clear ECC mode */
- pci_write_config32(ctrl->f0, DRC, data32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);
write32(BAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
@@ -1320,13 +1320,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
}
/* Bring memory subsystem on line */
- data32 = pci_read_config32(ctrl->f0, 0x98);
+ data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
data32 |= (1 << 31);
- pci_write_config32(ctrl->f0, 0x98, data32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32);
/* wait for completion */
print_debug("Waiting for mem complete\r\n");
while(1) {
- data32 = pci_read_config32(ctrl->f0, 0x98);
+ data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
@@ -1336,17 +1336,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* 0x7c DRC */
drc |= (1 << 29);
data32 = drc & ~(3 << 20); /* clear ECC mode */
- pci_write_config32(ctrl->f0, DRC, data32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);
/* Set the ecc mode */
- pci_write_config32(ctrl->f0, DRC, drc);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc);
/* Enable memory scrubbing */
/* 0x52 MCHSCRB */
- data16 = pci_read_config16(ctrl->f0, MCHSCRB);
+ data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), MCHSCRB);
data16 &= ~0x0f;
data16 |= ((2 << 2) | (2 << 0));
- pci_write_config16(ctrl->f0, MCHSCRB, data16);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16);
/* The memory is now setup, use it */
cache_lbmem(MTRR_TYPE_WRBACK);
diff --git a/src/northbridge/intel/e7520/raminit.h b/src/northbridge/intel/e7520/raminit.h
index 183ace8385..9fcc3801bb 100644
--- a/src/northbridge/intel/e7520/raminit.h
+++ b/src/northbridge/intel/e7520/raminit.h
@@ -4,9 +4,9 @@
#define DIMM_SOCKETS 4
struct mem_controller {
unsigned node_id;
- device_t f0, f1, f2, f3;
- uint16_t channel0[DIMM_SOCKETS];
- uint16_t channel1[DIMM_SOCKETS];
+ // device_t f0, f1, f2, f3;
+ u16 channel0[DIMM_SOCKETS];
+ u16 channel1[DIMM_SOCKETS];
};
#endif /* RAMINIT_H */
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index c7efb51791..80ee22c22a 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -31,16 +31,14 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/vx800/vx800.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
-#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "driving_clk_phase_data.c"
@@ -573,7 +571,7 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav
unsigned v_esp;
__asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)
);
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp=");
@@ -589,7 +587,7 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav
// it seems that cpu_reset is not used before this, so I just reset it, (this is because the s3 resume, setting in mtrr and copy data may destroy
//stack
cpu_reset = 0;
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
#else
print_debug("cpu_reset = ");
@@ -641,7 +639,7 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav
} else {
print_debug("Use Ram as Stack now - \r\n");
}
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = ");
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 13:14:49 +0000