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-rw-r--r--src/northbridge/intel/haswell/early_init.c22
-rw-r--r--src/northbridge/intel/haswell/raminit.c17
2 files changed, 5 insertions, 34 deletions
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 505fbf1125..681af42adb 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -29,20 +29,6 @@
static void haswell_setup_bars(void)
{
- /* Setting up Southbridge. In the northbridge code. */
- printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
-
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
-
- printk(BIOS_DEBUG, " done.\n");
-
- printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
- RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
- outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
- printk(BIOS_DEBUG, " done.\n");
-
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
@@ -62,14 +48,6 @@ static void haswell_setup_bars(void)
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
printk(BIOS_DEBUG, " done.\n");
-
-#if CONFIG_ELOG_BOOT_COUNT
- /* Increment Boot Counter except when resuming from S3 */
- if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
- ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
- return;
- boot_count_increment();
-#endif
}
static void haswell_setup_graphics(void)
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 0c68e60707..e2b085b3fd 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -32,8 +32,6 @@
#include "pei_data.h"
#include "haswell.h"
-/* Management Engine is in the southbridge */
-#include "southbridge/intel/lynxpoint/me.h"
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
#else
@@ -152,12 +150,6 @@ void sdram_initialize(struct pei_data *pei_data)
struct sys_info sysinfo;
unsigned long entry;
- report_platform_info();
-
- /* Wait for ME to be ready */
- intel_early_me_init();
- intel_early_me_uma_size();
-
printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
memset(&sysinfo, 0, sizeof(sysinfo));
@@ -216,8 +208,6 @@ void sdram_initialize(struct pei_data *pei_data)
version >> 24 , (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
- intel_early_me_status();
-
report_memory_config();
/* S3 resume: don't save scrambler seed or MRC data */
@@ -232,7 +222,10 @@ struct cbmem_entry *get_cbmem_toc(void)
unsigned long get_top_of_ram(void)
{
- /* Base of TSEG is top of usable DRAM */
+ /*
+ * Base of TSEG is top of usable DRAM below 4GiB. The register has
+ * 1 MiB alignement.
+ */
u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
- return (unsigned long) tom;
+ return (unsigned long) tom & ~((1 << 20) - 1);
}