diff options
Diffstat (limited to 'src/northbridge')
88 files changed, 884 insertions, 884 deletions
diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c index 567790cede..c5506eaca5 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_conf.c +++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c @@ -316,7 +316,7 @@ static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) return carry_over; } -#endif +#endif #endif // CONFIG_AMDMCT diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h index 580f27831b..283e32e235 100644 --- a/src/northbridge/amd/amdk8/amdk8_f.h +++ b/src/northbridge/amd/amdk8/amdk8_f.h @@ -87,7 +87,7 @@ #define DRAM_TIMING_LOW 0x88 #define DTL_TCL_SHIFT 0 #define DTL_TCL_MASK 7 -#define DTL_TCL_BASE 1 +#define DTL_TCL_BASE 1 #define DTL_TCL_MIN 3 #define DTL_TCL_MAX 6 #define DTL_TRCD_SHIFT 4 @@ -125,7 +125,7 @@ #define DTL_TRRD_BASE 2 #define DTL_TRRD_MIN 2 #define DTL_TRRD_MAX 5 -#define DTL_MemClkDis_SHIFT 24 /* Channel A */ +#define DTL_MemClkDis_SHIFT 24 /* Channel A */ #define DTL_MemClkDis3 (1 << 26) #define DTL_MemClkDis2 (1 << 27) #define DTL_MemClkDis1 (1 << 28) @@ -135,16 +135,16 @@ #define DTL_MemClkDis0_S1g1 (0xa2 << 24) /* DTL_MemClkDis for m2 and s1g1 is different */ - + #define DRAM_TIMING_HIGH 0x8c #define DTH_TRWTTO_SHIFT 4 #define DTH_TRWTTO_MASK 7 -#define DTH_TRWTTO_BASE 2 +#define DTH_TRWTTO_BASE 2 #define DTH_TRWTTO_MIN 2 #define DTH_TRWTTO_MAX 9 #define DTH_TWTR_SHIFT 8 #define DTH_TWTR_MASK 3 -#define DTH_TWTR_BASE 0 +#define DTH_TWTR_BASE 0 #define DTH_TWTR_MIN 1 #define DTH_TWTR_MAX 3 #define DTH_TWRRD_SHIFT 10 @@ -154,7 +154,7 @@ #define DTH_TWRRD_MAX 3 #define DTH_TWRWR_SHIFT 12 #define DTH_TWRWR_MASK 3 -#define DTH_TWRWR_BASE 1 +#define DTH_TWRWR_BASE 1 #define DTH_TWRWR_MIN 1 #define DTH_TWRWR_MAX 3 #define DTH_TRDRD_SHIFT 14 @@ -167,7 +167,7 @@ #define DTH_TREF_7_8_US 2 #define DTH_TREF_3_9_US 3 #define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */ -#define DTH_TRFC_MASK 7 +#define DTH_TRFC_MASK 7 #define DTH_TRFC_75_256M 0 #define DTH_TRFC_105_512M 1 #define DTH_TRFC_127_5_1G 2 @@ -185,12 +185,12 @@ #define DCL_DramTerm_No 0 #define DCL_DramTerm_75_OH 1 #define DCL_DramTerm_150_OH 2 -#define DCL_DramTerm_50_OH 3 +#define DCL_DramTerm_50_OH 3 #define DCL_DrvWeak (1<<7) #define DCL_ParEn (1<<8) #define DCL_SelfRefRateEn (1<<9) #define DCL_BurstLength32 (1<<10) -#define DCL_Width128 (1<<11) +#define DCL_Width128 (1<<11) #define DCL_X4Dimm_SHIFT 12 #define DCL_X4Dimm_MASK 0xf #define DCL_UnBuffDimm (1<<16) @@ -312,7 +312,7 @@ #define DATC_CkeFineDelay_MASK 0x1f #define DATC_CkeFineDelay_BASE 0 #define DATC_CkeFineDelay_MIN 0 -#define DATC_CkeFineDelay_MAX 31 +#define DATC_CkeFineDelay_MAX 31 #define DATC_CkeSetup (1<<5) #define DATC_CsOdtFineDelay_SHIFT 8 #define DATC_CsOdtFineDelay_MASK 0x1f @@ -320,7 +320,7 @@ #define DATC_CsOdtFineDelay_MIN 0 #define DATC_CsOdtFineDelay_MAX 31 #define DATC_CsOdtSetup (1<<13) -#define DATC_AddrCmdFineDelay_SHIFT 16 +#define DATC_AddrCmdFineDelay_SHIFT 16 #define DATC_AddrCmdFineDelay_MASK 0x1f #define DATC_AddrCmdFineDelay_BASE 0 #define DATC_AddrCmdFineDelay_MIN 0 @@ -361,7 +361,7 @@ #define DRAM_DQS_RECV_ENABLE_TIME2 0x16 #define DRAM_DQS_RECV_ENABLE_TIME3 0x19 -/* there are index 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39 +/* there are index 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39 that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19 */ #define DRAM_CTRL_MISC 0xa0 @@ -417,7 +417,7 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, #define SCRUB_655_4us 15 #define SCRUB_1_31ms 16 #define SCRUB_2_62ms 17 -#define SCRUB_5_24ms 18 +#define SCRUB_5_24ms 18 #define SCRUB_10_49ms 19 #define SCRUB_20_97ms 20 #define SCRUB_42ms 21 @@ -530,7 +530,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) unsigned needs_reset = 0; - if(sysinfo->nodes == 1) return; // in case only one cpu installed + if(sysinfo->nodes == 1) return; // in case only one cpu installed for(i=1; i<sysinfo->nodes; i++) { /* Skip everything if I don't have any memory on this controller */ @@ -563,7 +563,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) #ifdef __PRE_RAM__ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n"); #else - printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); + printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); #endif switch(sysinfo->mem_trained[i]) { case 0: //don't need train @@ -581,7 +581,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) print_debug("mem trained failed\n"); soft_reset(); #else - printk(BIOS_DEBUG, "mem trained failed\n"); + printk(BIOS_DEBUG, "mem trained failed\n"); hard_reset(); #endif } diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c index e42158d92a..13c72fe846 100644 --- a/src/northbridge/amd/amdk8/exit_from_self.c +++ b/src/northbridge/amd/amdk8/exit_from_self.c @@ -56,7 +56,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, printk(BIOS_DEBUG, "before resume errata #%d\n", (is_post_rev_g) ? 270 : 125); - /* + /* 1. Restore memory controller registers as normal. 2. Set the DisAutoRefresh bit (Dev:2x8C[18]). (270 only) 3. Set the EnDramInit bit (Dev:2x7C[31]), clear all other bits in the same register). diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 18b3109cf6..5d51f036cb 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -4,7 +4,7 @@ * devices which is done by the kernel * * written in 2003 by Eric Biederman - * + * * - Athlon64 workarounds by Stefan Reinauer * - "reset once" logic by Yinghai Lu */ @@ -24,7 +24,7 @@ /** * @brief Read resources for AGP aperture * - * @param + * @param * * There is only one AGP aperture resource needed. The resoruce is added to * the northbridge of BSP. @@ -64,7 +64,7 @@ static void mcf3_read_resources(device_t dev) static void set_agp_aperture(device_t dev) { struct resource *resource; - + resource = probe_resource(dev, 0x94); if (resource) { device_t pdev; @@ -78,7 +78,7 @@ static void set_agp_aperture(device_t dev) /* Get the base address */ gart_base = ((resource->base) >> 25) & 0x00007fff; - + /* Update the other northbriges */ pdev = 0; while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) { @@ -90,7 +90,7 @@ static void set_agp_aperture(device_t dev) /* Don't set the GART Table base address */ pci_write_config32(pdev, 0x98, 0); - + /* Report the resource has been stored... */ report_resource_stored(pdev, resource, " <gart>"); } @@ -111,7 +111,7 @@ static void misc_control_init(struct device *dev) uint32_t cmd, cmd_ref; int needs_reset; struct device *f0_dev; - + printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); needs_reset = 0; @@ -125,7 +125,7 @@ static void misc_control_init(struct device *dev) if (is_cpu_pre_c0()) { /* Errata 58 - * Disable CPU low power states C2, C1 and throttling + * Disable CPU low power states C2, C1 and throttling */ cmd = pci_read_config32(dev, 0x80); cmd &= ~(1<<0); @@ -136,7 +136,7 @@ static void misc_control_init(struct device *dev) pci_write_config32(dev, 0x84, cmd ); /* Errata 66 - * Limit the number of downstream posted requests to 1 + * Limit the number of downstream posted requests to 1 */ cmd = pci_read_config32(dev, 0x70); if ((cmd & (3 << 0)) != 2) { @@ -164,7 +164,7 @@ static void misc_control_init(struct device *dev) struct device *f2_dev; uint32_t dcl; f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2); - /* Errata 98 + /* Errata 98 * Set Clk Ramp Hystersis to 7 * Clock Power/Timing Low */ @@ -192,7 +192,7 @@ static void misc_control_init(struct device *dev) reg = 0x98 + (link * 0x20); link_type = pci_read_config32(f0_dev, reg); /* Only handle coherent link here please */ - if ((link_type & (LinkConnected|InitComplete|NonCoherent)) + if ((link_type & (LinkConnected|InitComplete|NonCoherent)) == (LinkConnected|InitComplete)) { cmd &= ~(0xff << (link *8)); diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index ad257d0ed6..7ad1b8004c 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -567,7 +567,7 @@ static int is_opteron(const struct mem_controller *ctrl) { /* Test to see if I am an Opteron. Socket 939 based Athlon64 * have dual channel capability, too, so we need a better test - * for Opterons. + * for Opterons. * However, all code uses is_opteron() to find out whether to * use dual channel, so if we really check for opteron here, we * need to fix up all code using this function, too. diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 6872883416..b89aa38d6a 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -393,7 +393,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 110 = 8 bus clocks * 111 = 9 bus clocks * [ 7: 7] Reserved - * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, + * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, * minium write-to-read delay when both access the same chip select) * 00 = Reserved * 01 = 1 bus clocks @@ -525,7 +525,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * registered DIMM is present * [19:19] Reserved * [20:20] SlowAccessMode (Slow Access Mode (2T Mode)) - * 0 = DRAM address and control signals are driven for one + * 0 = DRAM address and control signals are driven for one * MEMCLK cycle * 1 = One additional MEMCLK of setup time is provided on all * DRAM address and control signals except CS, CKE, and ODT; @@ -720,7 +720,7 @@ static int is_opteron(const struct mem_controller *ctrl) { /* Test to see if I am an Opteron. M2 and S1G1 support dual * channel, too, but only support unbuffered DIMMs so we need a - * better test for Opterons. + * better test for Opterons. * However, all code uses is_opteron() to find out whether to * use dual channel, so if we really check for opteron here, we * need to fix up all code using this function, too. @@ -1221,7 +1221,7 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl) csbase = value; canidate = index; } - + /* See if I have found a new canidate */ if (csbase == 0) { break; @@ -1640,7 +1640,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) /*15*/ 200, 160, 120, 100, }; - + int index; msr_t msr; @@ -1659,7 +1659,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) unsigned fid_start; msr = rdmsr(0xc0010015); fid_start = (msr.lo & (0x3f << 24)); - + index = fid_start>>25; } @@ -1843,7 +1843,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * continue; } } - + } /* Make a second pass through the dimms and disable * any that cannot support the selected memclk and cas latency. @@ -2060,7 +2060,7 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me if (clocks < TT_MIN) { clocks = TT_MIN; } - + if (clocks > TT_MAX) { printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX); clocks = TT_MAX; @@ -3001,7 +3001,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, #else int suspend = 0; #endif - + #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 unsigned cpu_f0_f1[8]; /* FIXME: How about 32 node machine later? */ diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 7b453bfc09..c56e51deb0 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -436,7 +436,7 @@ static uint16_t get_exact_T1000(unsigned i) unsigned fid_start; msr = rdmsr(0xc0010015); fid_start = (msr.lo & (0x3f << 24)); - + index = fid_start>>25; } @@ -600,12 +600,12 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st } for ( ; (channel < 2) && (!Errors); channel++) - { - print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); - - /* for each rank */ - /* there are four recriver pairs, loosely associated with CS */ - for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) + { + print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); + + /* for each rank */ + /* there are four recriver pairs, loosely associated with CS */ + for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) { unsigned index=(receiver>>1) * 3 + 0x10; diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index 042bc9949b..82622cdc4c 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -231,7 +231,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max) unsigned where; unsigned long reg; #if 0 - prink(BIOS_DEBUG, "%08x <- %08x\n", + prink(BIOS_DEBUG, "%08x <- %08x\n", register_values[i], register_values[i+2]); #endif where = register_values[i]; diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index fe4ae8c30c..3c4fa89e89 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -3391,7 +3391,7 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat, u8 max_dimms; // FIXME: skip for Ax - + dev = pDCTstat->dev_dct; /* Tri-state unused ODTs when motherboard termination is available */ diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index 1b0214d9fd..1176744c87 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -40,10 +40,10 @@ static void enable_shadow(device_t dev) write32(GX_BASE+BC_XMAP_3, 0x77777777); } -static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); - + optimize_xbus(dev); enable_shadow(dev); printk(BIOS_SPEW, "Calling enable_cache()\n"); @@ -63,7 +63,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver northbridge_driver __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_CYRIX, - .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, + .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, }; static void ram_resource(device_t dev, unsigned long index, @@ -132,7 +132,7 @@ static void pci_domain_set_resources(device_t dev) continue; ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2); } - + tomk = ramreg << 10; /* Sort out the framebuffer size */ @@ -172,7 +172,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { @@ -211,5 +211,5 @@ static void enable_dev(struct device *dev) struct chip_operations northbridge_amd_gx1_ops = { CHIP_NAME("AMD GX1 Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/northbridge/amd/gx1/raminit.c b/src/northbridge/amd/gx1/raminit.c index f61a69b4f8..8525ce4d1f 100644 --- a/src/northbridge/amd/gx1/raminit.c +++ b/src/northbridge/amd/gx1/raminit.c @@ -12,7 +12,7 @@ U.S. Government has rights to use, reproduce, and distribute this SOFTWARE. The public may copy, distribute, prepare derivative works and publicly display this SOFTWARE without charge, provided that this Notice and any statement of authorship are reproduced on all copies. -Neither the Government nor the University makes any warranty, express +Neither the Government nor the University makes any warranty, express or implied, or assumes any liability or responsibility for the use of this SOFTWARE. If SOFTWARE is modified to produce derivative works, such modified SOFTWARE should be clearly marked, so as not to confuse @@ -22,7 +22,7 @@ it with the version available from LANL. * rminnich@lanl.gov */ -/* SDRAM initialization for GX1 - translated from Christer Weinigel's +/* SDRAM initialization for GX1 - translated from Christer Weinigel's assembler version into C. Hamish Guthrie 10/4/2005 hamish@prodigi.ch @@ -53,7 +53,7 @@ unsigned int tval, i; setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval); outb(0x72, 0x80); } - + void enable_dimm(void) { @@ -93,12 +93,12 @@ unsigned int tval, i; tval &= ~PROGRAM_SDRAM; setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval); - /* Refresh memory again */ + /* Refresh memory again */ tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1); tval |= RFSHTST; for(i=0; i>NUM_REFRESH; i++) setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval); - + for(i=0; i<2000; i++) outb(0, 0xed); outb(0x74, 0x80); @@ -132,7 +132,7 @@ int failed_flag = 1; return (0x0070 << dimm_shift); else return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_SZ << dimm_shift)); - + } static unsigned int module_banks(int dimm_shift) @@ -229,7 +229,7 @@ unsigned int probe_config; #endif return(page_size_config << dimm_shift); } - + temp = ~(DIMM_PG_SZ << dimm_shift); probe_config = getGX1Mem(GX_BASE + MC_BANK_CFG); @@ -300,23 +300,23 @@ static int size_memory(int dimm_shift, unsigned int mem_config) mem_config &= (~(DIMM_MOD_BNK << dimm_shift)); mem_config |= (module_banks(dimm_shift)); - + print_debug(" Module Banks: "); print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30); print_debug("\n"); mem_config &= (~(DIMM_SZ << dimm_shift)); mem_config |= (size_dimm(dimm_shift)); - + print_debug(" DIMM size: "); - print_debug_hex32(1 << + print_debug_hex32(1 << ((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22); print_debug("\n"); return (mem_config); } -static void sdram_init(void) +static void sdram_init(void) { unsigned int mem_config = 0x00700070; @@ -327,7 +327,7 @@ unsigned int mem_config = 0x00700070; setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */ setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00700070); /* No DIMMS installed */ setGX1Mem(GX_BASE + MC_SYNC_TIM1, 0x3a733225); /* LTMODE=3, RC=10, RAS=7, RP=3, RCD=3, RRD=2, DPL=2 */ - setGX1Mem(GX_BASE + MC_BANK_CFG, 0x57405740); /* Largest DIMM size + setGX1Mem(GX_BASE + MC_BANK_CFG, 0x57405740); /* Largest DIMM size 0x4000 -- 2 module banks 0x1000 -- 4 component banks 0x0700 -- DIMM size 512MB diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c index 620f56452d..f0b99e7e9d 100644 --- a/src/northbridge/amd/gx2/chipsetinit.c +++ b/src/northbridge/amd/gx2/chipsetinit.c @@ -61,7 +61,7 @@ static struct msrinit CS5536_CLOCK_GATING_TABLE[] = { #ifdef UNUSED_CODE struct acpiinit { - unsigned short ioreg; + unsigned short ioreg; unsigned long regdata; unsigned short iolen; }; @@ -116,21 +116,21 @@ static void pmChipsetInit(void) port = (PMLogic_BASE + 0x034); val = 0x0A0 ; /* 5ms*/ outl(val, port); - + /* PM_WKD*/ port = (PMLogic_BASE + 0x030); outl(val, port); - + /* PM_SED*/ port = (PMLogic_BASE + 0x014); val = 0x04601 ; /* 5ms*/ outl(val, port); - + /* PM_SIDD*/ port = (PMLogic_BASE + 0x020); val = 0x08C02 ; /* 10ms*/ outl(val, port); - + /* GPIO24 OUT_AUX1 function is the external signal for 5535's * vsb_working_aux which is de-asserted when 5535 enters Standby (S3 or * S5) state. On Hawk, GPIO24 controls all voltage rails except Vmem @@ -154,7 +154,7 @@ static void pmChipsetInit(void) * Programming of GPIO11 will be done by VSA PM code. During VSA * Init. BIOS writes PM Core Virual Register indicating if S1 Clocks * should be On or Off. This is based on a Setup item. We do not want - * to leave GPIO11 enabled because of a Hawk board problem. With + * to leave GPIO11 enabled because of a Hawk board problem. With * GPIO11 enabled in S3, something is back-driving GPIO11 causing it * to float to 1.6-1.7V. */ @@ -188,7 +188,7 @@ static uint32_t FlashPort[] = { * ChipsetFlashSetup * * Flash LBARs need to be setup before VSA init so the PCI BARs have - * correct size info. Call this routine only if flash needs to be + * correct size info. Call this routine only if flash needs to be * configured (don't call it if you want IDE). * **************************************************************************/ @@ -240,16 +240,16 @@ static void ChipsetFlashSetup(void) } - + /**************************************************************************** - * + * * ChipsetGeodeLinkInit * * Handle chipset specific GeodeLink settings here. * Called from GeodeLink init code. - * + * ****************************************************************************/ -static void +static void ChipsetGeodeLinkInit(void) { msr_t msr; @@ -269,7 +269,7 @@ ChipsetGeodeLinkInit(void) return; totalmem = sizeram() << 20 - 1; - totalmem >>= 12; + totalmem >>= 12; totalmem = ~totalmem; totalmem &= 0xfffff; msr.lo = totalmem; @@ -292,7 +292,7 @@ gx2_chipsetinit (struct northbridge_amd_gx2_config *nb) printk(BIOS_DEBUG, "Companion is a %s\n", is_5536()?"CS5536":"CS5535"); #ifdef UNUSED_CODE - /* we hope NEVER to be in coreboot when S3 resumes + /* we hope NEVER to be in coreboot when S3 resumes if (! IsS3Resume()) */ { struct acpiinit *aci = acpi_init_table; @@ -319,14 +319,14 @@ gx2_chipsetinit (struct northbridge_amd_gx2_config *nb) msrnum = MSR_SB_USB2 + 8; wrmsr(msrnum, msr); } - + /* set hd IRQ */ outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE); outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT); /* Allow IO read and writes during a ATA DMA operation. */ /* This could be done in the HD rom but do it here for easier debugging. */ - + msrnum = ATA_SB_GLD_MSR_ERR; msr = rdmsr(msrnum); msr.lo &= ~0x100; diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c index a30ba78373..e59a838afe 100644 --- a/src/northbridge/amd/gx2/grphinit.c +++ b/src/northbridge/amd/gx2/grphinit.c @@ -4,7 +4,7 @@ #include <device/device.h> #include "chip.h" #include "northbridge.h" - + // FIXME handle UMA properly. #define VIDEO_MB 8 // MB of video memory diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index e74a8e33f8..98acbc9f95 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -19,7 +19,7 @@ #define NORTHBRIDGE_FILE "northbridge.c" -/* todo: add a resource record. We don't do this here because this may be called when +/* todo: add a resource record. We don't do this here because this may be called when * very little of the platform is actually working. */ int @@ -128,7 +128,7 @@ static void irq_init_steering(struct device *dev, u16 irq_map) { printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map); /* The IRQ steering values (in hex) are effectively dcba, where: - * <a> represents the IRQ for INTA, + * <a> represents the IRQ for INTA, * <b> represents the IRQ for INTB, * <c> represents the IRQ for INTC, and * <d> represents the IRQ for INTD. @@ -146,10 +146,10 @@ static void irq_init_steering(struct device *dev, u16 irq_map) { /* * setup_gx2_cache * - * Returns the amount of memory (in KB) available to the system. This is the + * Returns the amount of memory (in KB) available to the system. This is the * total amount of memory less the amount of memory reserved for SMM use. * - */ + */ static int setup_gx2_cache(void) { @@ -200,13 +200,13 @@ setup_gx2(void) membytes = size_kb * 1024; /* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST! - * so it is safe to use. You should NOT at this point call - * sizeram() directly. + * so it is safe to use. You should NOT at this point call + * sizeram() directly. */ /* we need to set 0x10000028 and 0x40000029 */ /* - * These two descriptors cover the range from 1 MB (0x100000) to + * These two descriptors cover the range from 1 MB (0x100000) to * SYSTOP (a.k.a. TOM, or Top of Memory) */ @@ -271,16 +271,16 @@ setup_gx2(void) static void enable_shadow(device_t dev) { - + } -static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { unsigned long m; struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); - + enable_shadow(dev); irq_init_steering(dev, nb->irqmap); @@ -421,7 +421,7 @@ static void pci_domain_set_resources(device_t dev) continue; ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2); } - + tomk = ramreg << 10; /* Sort out the framebuffer size */ @@ -455,7 +455,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { @@ -516,5 +516,5 @@ static void enable_dev(struct device *dev) struct chip_operations northbridge_amd_gx2_ops = { CHIP_NAME("AMD GX (previously GX2) Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 4ad5af23bc..7053f5e5d9 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -126,14 +126,14 @@ ShadowInit(struct gliutable *gl) msr = rdmsr(gl->desc_name); if (msr.lo == 0) { - writeglmsr(gl); + writeglmsr(gl); } } -/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here. +/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here. * CLEAN ME UP */ -/* yes, this duplicates later code, but it seems that is how they want it done. +/* yes, this duplicates later code, but it seems that is how they want it done. */ static void SysmemInit(struct gliutable *gl) @@ -141,8 +141,8 @@ SysmemInit(struct gliutable *gl) msr_t msr; int sizembytes, sizebytes; - /* - * Figure out how much RAM is in the machine and alocate all to the + /* + * Figure out how much RAM is in the machine and alocate all to the * system. We will adjust for SMM and DMM now and Frame Buffer later. */ sizembytes = sizeram(); @@ -165,7 +165,7 @@ SysmemInit(struct gliutable *gl) msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); - + } static void DMMGL0Init(struct gliutable *gl) { @@ -188,11 +188,11 @@ DMMGL0Init(struct gliutable *gl) { msr.hi |= (DMM_OFFSET >> 24); msr.lo = DMM_OFFSET << 8; msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); - + } static void DMMGL1Init(struct gliutable *gl) { @@ -211,7 +211,7 @@ DMMGL1Init(struct gliutable *gl) { /* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */ printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__); msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); @@ -238,7 +238,7 @@ SMMGL0Init(struct gliutable *gl) { msr.lo = SMM_OFFSET << 8; msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); @@ -254,7 +254,7 @@ SMMGL1Init(struct gliutable *gl) { msr.hi |= (SMM_OFFSET >> 24); msr.lo = SMM_OFFSET << 8; msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); @@ -265,31 +265,31 @@ GLIUInit(struct gliutable *gl){ while (gl->desc_type != GL_END){ switch(gl->desc_type){ - default: + default: /* For Unknown types: Write then read MSR */ writeglmsr(gl); case SC_SHADOW: /* Check for a Shadow entry*/ ShadowInit(gl); break; - + case R_SYSMEM: /* check for a SYSMEM entry*/ SysmemInit(gl); break; - + case BMO_DMM: /* check for a DMM entry*/ DMMGL0Init(gl); break; - + case BM_DMM : /* check for a DMM entry*/ DMMGL1Init(gl); break; - + case BMO_SMM : /* check for a SMM entry*/ SMMGL0Init(gl); break; - + case BM_SMM : /* check for a SMM entry*/ - SMMGL1Init(gl); + SMMGL1Init(gl); break; } gl++; @@ -413,7 +413,7 @@ static void GLPCIInit(void){ /* */ /* 5535 NB Init*/ - /* */ + /* */ msrnum = GLPCI_ARB; msr = rdmsr(msrnum); msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET; @@ -432,19 +432,19 @@ static void GLPCIInit(void){ msr.lo &= ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT); msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT; - + msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT); msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT; - + msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT); msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT; - + msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT); msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT; - + msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT); msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT; - + msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT); msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT; wrmsr(msrnum, msr); @@ -478,7 +478,7 @@ static void GLPCIInit(void){ /* * Modified:*/ /* **/ /* ***************************************************************************/ -static void +static void ClockGatingInit (void){ msr_t msr; struct msrinit *gating = ClockGatingDefault; @@ -489,7 +489,7 @@ ClockGatingInit (void){ NOSTACK bx, GetNVRAMValueBX cmp al, TVALUE_CG_OFF je gatingdone - + cmp al, TVALUE_CG_DEFAULT jb allon ja performance @@ -517,7 +517,7 @@ performance: } -static void +static void GeodeLinkPriority(void){ msr_t msr; struct msrinit *prio = GeodeLinkPriorityTable; @@ -537,7 +537,7 @@ GeodeLinkPriority(void){ } - + /* * Get the GLIU0 shadow register settings * If the setShadow function is used then all shadow descriptors @@ -613,7 +613,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo) { msr_t msr; - + // Set the Enable Register. msr = rdmsr(GLPCI_REN); @@ -667,7 +667,7 @@ static void setShadow(uint64_t shadowSettings) * Destroys: * **************************************************************************/ -static void +static void shadowRom(void) { uint64_t shadowSettings = getShadow(); @@ -688,7 +688,7 @@ shadowRom(void) * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory - * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough + * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough * ***************************************************************************/ #define SYSMEM_RCONF_WRITETHROUGH 8 @@ -716,17 +716,17 @@ RCONFInit(void) while (1); } -// sysdescfound: +// sysdescfound: /* found the descriptor... get its contents */ msr = rdmsr(gl->desc_name); - /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the - * top 8 bits go into 0-7 of edx. + /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the + * top 8 bits go into 0-7 of edx. */ msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF); msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF; msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8 - + // Set Default SYSMEM region properties msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; // 8 (or ~8) @@ -739,7 +739,7 @@ RCONFInit(void) // Set ROMBASE cache properties. msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24)); - + // now program RCONF_DEFAULT wrmsr(CPU_RCONF_DEFAULT, msr); @@ -776,15 +776,15 @@ northbridgeinit(void) GLIUInit(gliutables[i]); GeodeLinkPriority(); - + shadowRom(); - - // GeodeROM ensures that the BIOS waits the required 1 second before + + // GeodeROM ensures that the BIOS waits the required 1 second before // allowing anything to access PCI // PCIDelay(); - + RCONFInit(); - + // The cacheInit function in GeodeROM tests cache and, among other things, // makes sure all INVD instructions are treated as WBINVD. We do this // because we've found some programs which require this behavior. @@ -792,7 +792,7 @@ northbridgeinit(void) msr = rdmsr(CPU_DM_CONFIG0); msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET; wrmsr(CPU_DM_CONFIG0, msr); - + /* Now that the descriptor to memory is set up.*/ /* The memory controller needs one read to synch its lines before it can be used.*/ i = *(int *) 0; diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index 898e31dcd4..c1b22a28a0 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -125,7 +125,7 @@ static unsigned int get_memory_speed(void) #define DEFAULT_MDIV 3 #define DEFAULT_VDIV 2 -#define DEFAULT_FBDIV 22 // 366/244 ; 24 400/266 018 ;300/200 +#define DEFAULT_FBDIV 22 // 366/244 ; 24 400/266 018 ;300/200 static void pll_reset(void) { @@ -134,10 +134,10 @@ static void pll_reset(void) unsigned SyncBits; // store the sync bits in up ebx // clear the Bypass bit - + // If the straps say we are in bypass and the syspll is not AND there are no software // bits set then FS2 or something set up the PLL and we should not change it. - + msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); msrGlcpSysRstpll.lo &= ~RSTPPL_LOWER_BYPASS_SET; wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); @@ -145,15 +145,15 @@ static void pll_reset(void) // If the "we've already been here" flag is set, don't reconfigure the pll if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) ) { // we haven't configured the PLL; do it now - + // Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the // correct Strap Table. post_code(POST_PLL_INIT); - + // configure for DDR msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT); wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); - + // Use Manual settings // UseManual: post_code(POST_PLL_MANUAL); @@ -161,7 +161,7 @@ static void pll_reset(void) // DIV settings manually entered. // ax = VDIV, upper eax = MDIV, upper ecx = FbDIV // use gs and fs since we don't need them. - + // ProgramClocks: // ax = VDIV, upper eax = MDIV, upper ecx = FbDIV // move everything into ebx @@ -174,7 +174,7 @@ static void pll_reset(void) // FbDIV MDIV_VDIV_FBDIV |= (plldiv2fbdiv[DEFAULT_FBDIV] << RSTPLL_UPPER_FBDIV_SHIFT); - // write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values + // write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT); wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); @@ -192,15 +192,15 @@ static void pll_reset(void) // Check for Bypass mode. if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET) { - // If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. + // If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET; } else { - // CheckPCIsync: + // CheckPCIsync: // If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater // look up the real divider... if we get a 0 we have serious problems - if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] % + if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] % (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) ) { SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET; @@ -234,13 +234,13 @@ static void pll_reset(void) msrGlcpSysRstpll.lo |= (RSTPPL_LOWER_PLL_RESET_SET + RSTPPL_LOWER_PD_SET); msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); - + // You should never get here..... The chip has reset. post_code(POST_PLL_RESET_FAIL); while (1); } // we haven't configured the PLL; do it now - + } // End of Goodrich version of pll_reset /////////////////////////////////////////////////////////////////////////////// diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index b1cb1af6b3..3f99cab8ee 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -61,7 +61,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) //print_debug("sdram_enable step 6\n"); /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet, - * it is documented in LX datasheet */ + * it is documented in LX datasheet */ /* load Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); msr.lo |= ((0x01 << 27) | 0x01); @@ -85,10 +85,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* load RDSYNC */ msr = rdmsr(0x2000001f); msr.hi = 0x000ff310; - /* the above setting is supposed to be good for "slow" ram. We have found that for - * some dram, at some clock rates, e.g. hynix at 366/244, this will actually + /* the above setting is supposed to be good for "slow" ram. We have found that for + * some dram, at some clock rates, e.g. hynix at 366/244, this will actually * cause errors. The fix is to just set it to 0x310. Tested on 3 boards - * with 3 different type of dram -- Hynix, PSC, infineon. + * with 3 different type of dram -- Hynix, PSC, infineon. * I am leaving this comment here so that at some future time nobody is tempted * to mess with this setting -- RGM, 9/2006 */ diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index 57a485eedc..09eba0791a 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_LX bool select HAVE_HIGH_TABLES select GEODE_VSA - + config VIDEO_MB int default 8 diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c index 85e6a45ba0..b245eea062 100644 --- a/src/northbridge/amd/lx/grphinit.c +++ b/src/northbridge/amd/lx/grphinit.c @@ -35,7 +35,7 @@ struct msrinit { }; static const struct msrinit geodelx_vga_msr[] = { - /* Enable the GLIU Memory routing to the hardware + /* Enable the GLIU Memory routing to the hardware * PDID1 : Port 4, GLIU0 * PBASE : 0x000A0 * PMASK : 0xFFFE0 @@ -71,9 +71,9 @@ void graphics_init(void) /* SoftVG initialization */ printk(BIOS_DEBUG, "Graphics init...\n"); - + geodelx_vga_msr_init(); - + /* Call SoftVG with the main configuration parameters. */ /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */ @@ -94,7 +94,7 @@ void graphics_init(void) * so we can add the real value in megabytes */ - wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | + wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK); vrWrite(wClassIndex, wData); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4dd29d134f..6eba99d9df 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -262,7 +262,7 @@ void print_conf(void) #endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR } -/* todo: add a resource record. We don't do this here because this may be called when +/* todo: add a resource record. We don't do this here because this may be called when * very little of the platform is actually working. */ int sizeram(void) diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 75d77f0305..9014fb1de3 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -22,9 +22,9 @@ #include <spd.h> #include "southbridge/amd/cs5536/cs5536.h" -static const unsigned char NumColAddr[] = { - 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F +static const unsigned char NumColAddr[] = { + 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F }; static void banner(const char *s) @@ -35,8 +35,8 @@ static void banner(const char *s) static void hcf(void) { print_emerg("DIE\n"); - /* this guarantees we flush the UART fifos (if any) and also - * ensures that things, in general, keep going so no debug output + /* this guarantees we flush the UART fifos (if any) and also + * ensures that things, in general, keep going so no debug output * is lost */ while (1) @@ -231,7 +231,7 @@ static void set_refresh_rate(void) } msr = rdmsr(MC_CF07_DATA); - msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16) + msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16) << CF07_LOWER_REF_INT_SHIFT; wrmsr(MC_CF07_DATA, msr); } @@ -649,7 +649,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* If both Page Size = "Not Installed" we have a problems and should halt. */ msr = rdmsr(MC_CF07_DATA); - if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == + if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) { print_emerg("No memory in the system\n"); post_code(ERROR_NO_DIMMS); diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c index 500ea3e138..c116cb6296 100644 --- a/src/northbridge/intel/e7501/debug.c +++ b/src/northbridge/intel/e7501/debug.c @@ -16,8 +16,8 @@ static void print_debug_pci_dev(unsigned dev) static inline void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -35,7 +35,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - + for(i = 0; i < 256; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -61,8 +61,8 @@ static void dump_pci_device(unsigned dev) static inline void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -104,8 +104,8 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); #else - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); #endif @@ -141,8 +141,8 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); #else - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); #endif @@ -188,7 +188,7 @@ static inline void dump_smbus_registers(void) print_debug_hex8(device); #endif for(j = 0; j < 256; j++) { - int status; + int status; unsigned char byte; status = smbus_read_byte(device, j); if (status < 0) { @@ -212,10 +212,10 @@ static inline void dump_smbus_registers(void) #endif } print_debug("\n"); - } + } } -static inline void dump_io_resources(unsigned port) +static inline void dump_io_resources(unsigned port) { int i; @@ -257,13 +257,13 @@ static inline void dump_mem(unsigned start, unsigned end) if((i & 0xf)==0) { #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "\n%08x:", i); -#else +#else print_debug("\n"); print_debug_hex32(i); print_debug(":"); #endif } -#if CONFIG_USE_PRINTK_IN_CAR +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); #else print_debug(" "); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index c3b373c926..a2e4b245ee 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -112,11 +112,11 @@ static void pci_domain_set_resources(device_t dev) remapbase_r = pci_read_config16(mc_dev, 0xc6); remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00); pci_write_config16(mc_dev, 0xc6, remapbase_r); - + remaplimit_r = pci_read_config16(mc_dev, 0xc8); remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00); pci_write_config16(mc_dev, 0xc8, remaplimit_r); - + /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, 640); @@ -145,7 +145,7 @@ static struct device_operations pci_domain_ops = { .init = 0, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = &pci_cf8_conf1, -}; +}; static void cpu_bus_init(device_t dev) { diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c index 9f757e0f79..ac3bd41866 100644 --- a/src/northbridge/intel/e7501/raminit.c +++ b/src/northbridge/intel/e7501/raminit.c @@ -1,9 +1,9 @@ /* This was originally for the e7500, modified for e7501 - * The primary differences are that 7501 apparently can + * The primary differences are that 7501 apparently can * support single channel RAM (i haven't tested), * CAS1.5 is no longer supported, The ECC scrubber * now supports a mode to zero RAM and init ECC in one step - * and the undocumented registers at 0x80 require new + * and the undocumented registers at 0x80 require new * (undocumented) values determined by guesswork and * comparison w/ OEM BIOS values. * Steven James 02/06/2003 @@ -17,7 +17,7 @@ #include <stdlib.h> #include "e7501.h" -// Uncomment this to enable run-time checking of DIMM parameters +// Uncomment this to enable run-time checking of DIMM parameters // for dual-channel operation // Unfortunately the code seems to chew up several K of space. //#define VALIDATE_DIMM_COMPATIBILITY @@ -52,10 +52,10 @@ struct dimm_size { /**********************************************************************************/ static const uint32_t refresh_frequency[] = { - /* Relative frequency (array value) of each E7501 Refresh Mode Select + /* Relative frequency (array value) of each E7501 Refresh Mode Select * (RMS) value (array index) * 0 == least frequent refresh (longest interval between refreshes) - * [0] disabled -> 0 + * [0] disabled -> 0 * [1] 15.6 usec -> 2 * [2] 7.8 usec -> 3 * [3] 64 usec -> 1 @@ -68,10 +68,10 @@ static const uint32_t refresh_frequency[] = { }; static const uint32_t refresh_rate_map[] = { - /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode + /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode * Select values (array value) * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 - * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and + * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and * 64 clock (481 ns) (7) refresh. * [0] == 15.625 us -> 15.6 us * [1] == 3.9 us -> 481 ns @@ -110,7 +110,7 @@ static const long constant_register_values[] = { */ // Not everyone wants to be Super Micro Computer, Inc. // The mainboard should set this if desired. - // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), + // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), /* Undocumented * (DRAM Read Timing Control, if similar to 855PM?) @@ -125,11 +125,11 @@ static const long constant_register_values[] = { * CAS 2.0 values taken from Intel BIOS settings, others are a guess * and may be terribly wrong. Old values preserved as comments until I * figure this out for sure. - * e7501 docs claim that CAS1.5 is unsupported, so it may or may not + * e7501 docs claim that CAS1.5 is unsupported, so it may or may not * work at all. * Steven James 02/06/2003 */ - /* NOTE: values now configured in configure_e7501_cas_latency() based + /* NOTE: values now configured in configure_e7501_cas_latency() based * on SPD info and total number of DIMMs (per Intel) */ @@ -168,8 +168,8 @@ static const long constant_register_values[] = { /* DRB - DRAM Row Boundary Registers * 0x60 - 0x6F * An array of 8 byte registers, which hold the ending - * memory address assigned to each pair of DIMMS, in 64MB - * granularity. + * memory address assigned to each pair of DIMMS, in 64MB + * granularity. */ // Conservatively say each row has 64MB of ram, we will fix this up later // NOTE: These defaults allow us to prime all of the DIMMs on the board @@ -178,7 +178,7 @@ static const long constant_register_values[] = { 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24), 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24), - /* DRA - DRAM Row Attribute Register + /* DRA - DRAM Row Attribute Register * 0x70 Row 0,1 * 0x71 Row 2,3 * 0x72 Row 4,5 @@ -312,7 +312,7 @@ static const long constant_register_values[] = { // .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), // .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8), - // Default to dual-channel mode, ECC, 1-clock address/cmd hold + // Default to dual-channel mode, ECC, 1-clock address/cmd hold // NOTE: configure_e7501_dram_controller_mode() configures further 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8), @@ -425,7 +425,7 @@ static const long constant_register_values[] = { 0xf4, 0x3f8ffffd, 0x40300002, #ifdef SUSPICIOUS_LOOKING_CODE - // SJM: Undocumented. + // SJM: Undocumented. // This will access D2:F0:0x50, is this correct?? 0x1050, 0xffffffcf, 0x00000030, #endif @@ -606,11 +606,11 @@ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) // Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate // Return Value: dimm_size - log2(number of bits) for each side of the DIMM // Description: Calculate the log base 2 size in bits of both DIMM sides. -// log2(# bits) = (# columns) + log2(data width) + +// log2(# bits) = (# columns) + log2(data width) + // (# rows) + log2(banks per SDRAM) // -// Note that it might be easier to use SPD byte 31 here, it has the -// DIMM size as a multiple of 4MB. The way we do it now we can size +// Note that it might be easier to use SPD byte 31 here, it has the +// DIMM size as a multiple of 4MB. The way we do it now we can size // both sides of an asymmetric dimm. // static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) @@ -653,7 +653,7 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) #ifdef VALIDATE_DIMM_COMPATIBILITY //---------------------------------------------------------------------------------- // Function: are_spd_values_equal -// Parameters: spd_byte_number - +// Parameters: spd_byte_number - // dimmN_address - SMBus addresses of DIMM sockets to interrogate // Return Value: 1 if both DIMM sockets report the same value for the specified // SPD parameter; 0 if the values differed or an error occurred. @@ -834,7 +834,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) //---------------------------------------------------------------------------------- // Function: do_ram_command -// Parameters: +// Parameters: // command - specifies the command to be sent to the DIMMs: // RAM_COMMAND_NOP - No Operation // RAM_COMMAND_PRECHARGE - Precharge all banks @@ -860,7 +860,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) dram_controller_mode |= command; pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - // RAM_COMMAND_NORMAL is an exception. + // RAM_COMMAND_NORMAL is an exception. // It affects only the memory controller and does not need to be "sent" to the DIMMs. if (command != RAM_COMMAND_NORMAL) { @@ -897,7 +897,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) // NOTE: 0x40 * 64 MB == 4 GB ASSERT(dimm_start_64M_multiple < 0x40); - // NOTE: 2^26 == 64 MB + // NOTE: 2^26 == 64 MB uint32_t dimm_start_address = dimm_start_64M_multiple << 26; @@ -921,7 +921,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) // Parameters: jedec_mode_bits - for mode register set & extended mode register set // commands, bits 0-12 contain the register value in JEDEC format. // Return Value: None -// Description: Set the mode register of all DIMMs. The proper CAS# latency +// Description: Set the mode register of all DIMMs. The proper CAS# latency // setting is added to the mode bits specified by the caller. // static void set_ram_mode(uint16_t jedec_mode_bits) @@ -954,11 +954,11 @@ static void set_ram_mode(uint16_t jedec_mode_bits) //---------------------------------------------------------------------------------- // Function: configure_dimm_row_boundaries -// Parameters: +// Parameters: // dimm_log2_num_bits - log2(number of bits) for each side of the DIMM -// total_dram_64M_multiple - total DRAM in the system (as a +// total_dram_64M_multiple - total DRAM in the system (as a // multiple of 64 MB) for DIMMs < dimm_index -// dimm_index - which DIMM pair is being processed +// dimm_index - which DIMM pair is being processed // (0..MAX_DIMM_SOCKETS_PER_CHANNEL) // Return Value: New multiple of 64 MB total DRAM in the system // Description: Configure the E7501's DRAM Row Boundary registers for the memory @@ -975,7 +975,7 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits ASSERT((dimm_log2_num_bits.side2 == 0) || (dimm_log2_num_bits.side2 >= 28)); - // In dual-channel mode, we are called only once for each pair of DIMMs. + // In dual-channel mode, we are called only once for each pair of DIMMs. // Each time we process twice the capacity of a single DIMM. // Convert single DIMM capacity to paired DIMM capacity @@ -994,7 +994,7 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1), total_dram_64M_multiple); - // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair + // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair // (as a multiple of 64 MB) to the total capacity of the system if (dimm_log2_num_bits.side2 >= 29) total_dram_64M_multiple += @@ -1021,12 +1021,12 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits // Function: configure_e7501_ram_addresses // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None -// Description: Program the E7501's DRAM row boundary addresses and its Top Of -// Low Memory (TOLM). If necessary, set up a remap window so we -// don't waste DRAM that ordinarily would lie behind addresses +// Description: Program the E7501's DRAM row boundary addresses and its Top Of +// Low Memory (TOLM). If necessary, set up a remap window so we +// don't waste DRAM that ordinarily would lie behind addresses // reserved for memory-mapped I/O. // static void configure_e7501_ram_addresses(const struct mem_controller @@ -1181,11 +1181,11 @@ static void initialize_ecc(void) // Function: configure_e7501_dram_timing // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None -// Description: Program the DRAM Timing register of the E7501 (except for CAS# -// latency, which is assumed to have been programmed already), based +// Description: Program the DRAM Timing register of the E7501 (except for CAS# +// latency, which is assumed to have been programmed already), based // on the parameters of the various installed DIMMs. // static void configure_e7501_dram_timing(const struct mem_controller *ctrl, @@ -1255,7 +1255,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, if (slowest_row_precharge > ((22 << 2) | (2 << 0))) die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks else if (slowest_row_precharge > (15 << 2)) - dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks + dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks else dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks @@ -1267,7 +1267,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0))) die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks else if (slowest_ras_cas_delay > (15 << 2)) - dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks + dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks else dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks @@ -1280,7 +1280,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, if (slowest_active_to_precharge_delay > 52) die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks else if (slowest_active_to_precharge_delay > 45) - dram_timing |= (0 << 9); // 46-52 ns: 7 clocks + dram_timing |= (0 << 9); // 46-52 ns: 7 clocks else if (slowest_active_to_precharge_delay > 37) dram_timing |= (1 << 9); // 38-45 ns: 6 clocks else @@ -1318,7 +1318,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, // Function: configure_e7501_cas_latency // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Determine the shortest CAS# latency that the E7501 and all DIMMs @@ -1475,7 +1475,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, // Function: configure_e7501_dram_controller_mode // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Configure the refresh interval so that we refresh no more often @@ -1583,7 +1583,7 @@ static void configure_e7501_dram_controller_mode(const struct // Function: configure_e7501_row_attributes // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Configure the E7501's DRAM Row Attributes (DRA) registers @@ -1636,7 +1636,7 @@ static void configure_e7501_row_attributes(const struct mem_controller //---------------------------------------------------------------------------------- // Function: enable_e7501_clocks -// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see +// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Enable clock signals for populated DIMM sockets and disable them @@ -1690,8 +1690,8 @@ static void RAM_RESET_DDR_PTR(void) // Description: Set E7501 registers that are either independent of DIMM specifics, // or establish default settings that will be overridden when we // learn the specifics. -// This sets PCI configuration registers to known good values based -// on the table 'constant_register_values', which are a triple of +// This sets PCI configuration registers to known good values based +// on the table 'constant_register_values', which are a triple of // configuration register offset, mask, and bits to set. // static void ram_set_d0f0_regs(void) @@ -1748,8 +1748,8 @@ static void write_8dwords(const uint32_t * src_addr, uint32_t dst_addr) // Parameters: None // Return Value: None // Description: Set the E7501's (undocumented) RCOMP registers. -// Per the 855PM datasheet and IXP2800 HW Initialization Reference -// Manual, RCOMP registers appear to affect drive strength, +// Per the 855PM datasheet and IXP2800 HW Initialization Reference +// Manual, RCOMP registers appear to affect drive strength, // pullup/pulldown offset, and slew rate of various signal groups. // Comments below are conjecture based on apparent similarity // between the E7501 and these two chips. @@ -1980,9 +1980,9 @@ static void sdram_enable(int controllers, // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard // Return Value: None -// Description: Configure SDRAM controller parameters that depend on -// characteristics of the DIMMs installed in the system. These -// characteristics are read from the DIMMs via the standard Serial +// Description: Configure SDRAM controller parameters that depend on +// characteristics of the DIMMs installed in the system. These +// characteristics are read from the DIMMs via the standard Serial // Presence Detect (SPD) interface. // static void sdram_set_spd_registers(const struct mem_controller *ctrl) @@ -2011,7 +2011,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) } /* NOTE: configure_e7501_ram_addresses() is NOT called here. - * We want to keep the default 64 MB/row mapping until sdram_enable() is called, + * We want to keep the default 64 MB/row mapping until sdram_enable() is called, * even though the default mapping is almost certainly incorrect. * The default mapping makes it easy to initialize all of the DIMMs * even if the total system memory is > 4 GB. @@ -2028,7 +2028,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard // Return Value: None -// Description: Do basic ram setup that does NOT depend on serial presence detect +// Description: Do basic ram setup that does NOT depend on serial presence detect // information (i.e. independent of DIMM specifics). // static void sdram_set_registers(const struct mem_controller *ctrl) diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h index 0d09414904..df0e9291a3 100644 --- a/src/northbridge/intel/e7501/raminit.h +++ b/src/northbridge/intel/e7501/raminit.h @@ -6,12 +6,12 @@ #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) struct mem_controller { - device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller + device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller // SMBus addresses of DIMM slots for each channel, // in order from closest to MCH to furthest away // 0 == not present - uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL]; + uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL]; uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; }; diff --git a/src/northbridge/intel/e7501/reset_test.c b/src/northbridge/intel/e7501/reset_test.c index 79a5cdaee1..1c0dad5ed9 100644 --- a/src/northbridge/intel/e7501/reset_test.c +++ b/src/northbridge/intel/e7501/reset_test.c @@ -7,12 +7,12 @@ */ static int bios_reset_detected(void) { uint32_t dword; - + dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - + if( (dword & DRC_DONE) != 0 ) { return 1; - } - + } + return 0; } diff --git a/src/northbridge/intel/e7520/memory_initialized.c b/src/northbridge/intel/e7520/memory_initialized.c index 133d1c4f88..d7a8048567 100644 --- a/src/northbridge/intel/e7520/memory_initialized.c +++ b/src/northbridge/intel/e7520/memory_initialized.c @@ -10,4 +10,4 @@ static inline int memory_initialized(void) //print_debug("\n"); return (drc & (1<<29)); -} +} diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index efb7f0263b..93604b6cf7 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -16,7 +16,7 @@ static unsigned int max_bus; -static void ram_resource(device_t dev, unsigned long index, +static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { struct resource *resource; @@ -195,7 +195,7 @@ static void mc_set_resources(device_t dev) static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/northbridge/intel/e7520/pciexp_porta.c b/src/northbridge/intel/e7520/pciexp_porta.c index 07440e368e..ab73a713c2 100644 --- a/src/northbridge/intel/e7520/pciexp_porta.c +++ b/src/northbridge/intel/e7520/pciexp_porta.c @@ -7,16 +7,16 @@ #include <arch/io.h> #include "chip.h" #include <reset.h> - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -58,5 +58,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA, }; - + diff --git a/src/northbridge/intel/e7520/pciexp_porta1.c b/src/northbridge/intel/e7520/pciexp_porta1.c index 26605df8ab..c79535fbb0 100644 --- a/src/northbridge/intel/e7520/pciexp_porta1.c +++ b/src/northbridge/intel/e7520/pciexp_porta1.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA1, }; - + diff --git a/src/northbridge/intel/e7520/pciexp_portb.c b/src/northbridge/intel/e7520/pciexp_portb.c index 668c665988..b20abdee6f 100644 --- a/src/northbridge/intel/e7520/pciexp_portb.c +++ b/src/northbridge/intel/e7520/pciexp_portb.c @@ -7,16 +7,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -38,5 +38,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PB, }; - + diff --git a/src/northbridge/intel/e7520/pciexp_portc.c b/src/northbridge/intel/e7520/pciexp_portc.c index fe55e661ec..d2706d1364 100644 --- a/src/northbridge/intel/e7520/pciexp_portc.c +++ b/src/northbridge/intel/e7520/pciexp_portc.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PC, }; - + diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index 836e6f8c7c..7f1b9d500a 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -33,13 +33,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl) /* CKDIS 0x8c disable clocks */ PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - /* 0x9c Device present and extended RAM control + /* 0x9c Device present and extended RAM control * DEVPRES is very touchy, hard code the initialization * of PCI-E ports here. */ PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG, - /* 0xc8 Remap RAM base and limit off */ + /* 0xc8 Remap RAM base and limit off */ PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000, /* ??? */ @@ -57,7 +57,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG, /* 0x14 */ - PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, + PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, }; int i; int max; @@ -122,7 +122,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - + low = spd_read_byte(device, 6); /* (low byte) */ if (low < 0) goto hw_err; value = value | (low & 0xff); @@ -169,7 +169,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask) { int i; int cum; - + for(i = cum = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; if (dimm_mask & (1 << i)) { @@ -233,7 +233,7 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) } -static int spd_set_row_attributes(const struct mem_controller *ctrl, +static int spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) { @@ -264,22 +264,22 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, reg += log2(value & 0xff); /* Get the device width and convert it to a power of two */ - value = spd_read_byte(ctrl->channel0[cnt], 13); + value = spd_read_byte(ctrl->channel0[cnt], 13); if (value < 0) goto hw_err; value = log2(value & 0xff); reg += value; if(reg < 27) goto hw_err; reg -= 27; reg += (value << 2); - + dra += reg << (cnt*8); value = spd_read_byte(ctrl->channel0[cnt], 5); if (value & 2) - dra += reg << ((cnt*8)+4); + dra += reg << ((cnt*8)+4); } /* 0x70 DRA */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra); goto out; val_err: @@ -293,7 +293,7 @@ hw_err: } -static int spd_set_drt_attributes(const struct mem_controller *ctrl, +static int spd_set_drt_attributes(const struct mem_controller *ctrl, long dimm_mask, uint32_t drc) { int value; @@ -305,23 +305,23 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, int latency; uint32_t index = 0; uint32_t index2 = 0; - static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; + static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; static const int latency_indicies[] = { 26, 23, 9 }; /* 0x78 DRT */ drt = pci_read_config32(PCI_DEV(0, 0x00, 0), DRT); drt &= 3; /* save bits 1:0 */ - + for(first_dimm = 0; first_dimm < 4; first_dimm++) { - if (dimm_mask & (1 << first_dimm)) + if (dimm_mask & (1 << first_dimm)) break; } - + /* get dimm type */ value = spd_read_byte(ctrl->channel0[first_dimm], 2); if(value == 8) { drt |= (3<<5); /* back to bark write turn around & cycle add */ - } + } drt |= (3<<18); /* Trasmax */ @@ -332,22 +332,22 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */ /* Compute the lowest cas latency supported */ latency = log2(reg) -2; - + /* Loop through and find a fast clock with a low latency */ for(index = 0; index < 3; index++, latency++) { if ((latency < 2) || (latency > 4) || (!(reg & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[cnt], + value = spd_read_byte(ctrl->channel0[cnt], latency_indicies[index]); - + if(value <= cycle_time[drc&3]) { if( latency > cas_latency) { cas_latency = latency; } break; - } + } } } index = (cas_latency-2); @@ -401,7 +401,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x03c) { drt |= (0<<10); @@ -411,7 +411,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, /* Tdal Write auto precharge recovery delay */ drt |= (1<<12); - + /* Trc TRS min */ if((index2&0x0ff00)<=0x03700) drt |= (0<<14); @@ -419,9 +419,9 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, drt |= (1<<14); else drt |= (2<<14); /* spd 41 */ - + drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0140000) { drt |= (0<<20); @@ -432,7 +432,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (3<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -446,14 +446,14 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else if(value <= 0x60) { /* 167 Mhz */ /* according to new documentation CAS latency is 00 - * for bits 3:2 for all 167 Mhz + * for bits 3:2 for all 167 Mhz drt |= ((index&3)<<2); */ /* set CAS latency */ if((index&0x0ff00)<=0x03000) { drt |= (1<<8); /* Trp RAS Precharg */ } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x030) { drt |= (0<<10); @@ -462,13 +462,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (2<<12); - + drt |= (2<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (2<<16); /* Twr not defined for DDR docs say 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0180000) { drt |= (0<<20); @@ -477,7 +477,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x0480000) { drt |= (0<<22); @@ -505,13 +505,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); - + drt |= (1<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (1<<16); /* Twr not defined for DDR docs say 1 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x01e0000) { drt |= (0<<20); @@ -520,7 +520,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -529,13 +529,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<22); } - + /* Based on CAS latency */ if(index&7) drt |= (0x099<<24); else drt |= (0x055<<24); - + } else { die("Invalid SPD 9 bus speed.\n"); @@ -547,7 +547,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, return(cas_latency); } -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, +static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, long dimm_mask) { int value; @@ -558,12 +558,12 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, unsigned char dram_type = 0xff; unsigned char ecc = 0xff; unsigned char rate = 62; - static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; + static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; static const unsigned char drc_rates[5] = {0,15,7,62,3}; static const unsigned char fsb_conversion[4] = {3,1,3,2}; /* 0x7c DRC */ - drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC); + drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC); for(cnt=0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; @@ -578,7 +578,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if (ecc == 1) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else if ( reg == 7 ) { if ( ecc == 0xff) { ecc = 1; @@ -586,7 +586,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if ( ecc > 1 ) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else { die("ERROR - RAM not DDR\n"); } @@ -650,7 +650,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, drc |= (fsb_conversion[value] << 2); drc &= ~(3 << 0); /* set the dram type */ drc |= (dram_type << 0); - + goto out; val_err: @@ -662,7 +662,7 @@ hw_err: return drc; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { long dimm_mask; @@ -681,7 +681,7 @@ static void do_delay(void) unsigned char b; for(i=0;i<16;i++) b=inb(0x80); -} +} static void pll_setup(uint32_t drc) { @@ -710,7 +710,7 @@ static void pll_setup(uint32_t drc) } mainboard_set_e7520_pll(pins); return; -} +} #define TIMEOUT_LOOPS 300000 @@ -724,7 +724,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) unsigned int dimm,i; unsigned int data32; unsigned int t4; - + /* Set up northbridge values */ /* ODT enable */ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xf0000180); @@ -741,10 +741,10 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) for(i=0;i<1;i++) { if((t4&0x0f) == 1) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00000010; /* EEES */ + data32 = 0x00000010; /* EEES */ break; } - if ( ((t4>>16)&0x0f) == 0 ) { + if ( ((t4>>16)&0x0f) == 0 ) { data32 = 0x00003132; /* EESS */ break; } @@ -757,7 +757,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) } if((t4&0x0f) == 2) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00003132; /* EEED */ + data32 = 0x00003132; /* EEED */ break; } if ( ((t4>>8)&0x0f) == 2 ) { @@ -784,14 +784,14 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, 0x83000003 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) break; } } -} +} static void set_receive_enable(const struct mem_controller *ctrl) { unsigned int i; @@ -799,7 +799,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) uint32_t recena=0; uint32_t recenb=0; - { + { unsigned int dimm; unsigned int edge; int32_t data32; @@ -817,7 +817,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) if(!(dimm&1)) { write32(BAR+DCALDATA+(17*4), 0x04020000); write32(BAR+DCALCSR, 0x83800004 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) @@ -825,7 +825,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) } if(i>=1000) continue; - + dcal_data32_0 = read32(BAR+DCALDATA + 0); dcal_data32_1 = read32(BAR+DCALDATA + 4); dcal_data32_2 = read32(BAR+DCALDATA + 8); @@ -914,7 +914,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) data32++; } /* test for frame edge cross overs */ - if((edge == 1) && (data32 > 12) && + if((edge == 1) && (data32 > 12) && (((recen+16)-data32) < 3)) { data32 = 0; cnt += 2; @@ -1063,15 +1063,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* FSB 200 DIMM 400 */ {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}}, }; - + static const uint32_t dqs_data[] = { - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); @@ -1101,24 +1101,24 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* 0x7c DRC */ pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); - + /* turn the clocks on */ /* 0x8c CKDIS */ pci_write_config16(PCI_DEV(0, 0x00, 0), CKDIS, 0x0000); - + /* 0x9a DDRCSR Take subsystem out of idle */ data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DDRCSR); data16 &= ~(7 << 12); data16 |= (3 << 12); /* use dual channel lock step */ pci_write_config16(PCI_DEV(0, 0x00, 0), DDRCSR, data16); - + /* program row size DRB */ spd_set_ram_size(ctrl, mask); /* program page size DRA */ spd_set_row_attributes(ctrl, mask); - /* program DRT timing values */ + /* program DRT timing values */ cas_latency = spd_set_drt_attributes(ctrl, mask, drc); for(i=0;i<8;i++) { /* loop throught each dimm to test for row */ @@ -1127,7 +1127,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); /* Apply NOP */ do_delay(); - + write32(BAR + 0x100, (0x03000000 | (i<<20))); write32(BAR+0x100, (0x83000000 | (i<<20))); @@ -1137,12 +1137,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 = read32(BAR+DCALCSR); } - + /* Apply NOP */ do_delay(); - for(cs=0;cs<8;cs++) { - write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); + for(cs=0;cs<8;cs++) { + write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); @@ -1150,7 +1150,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharg all banks */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1160,10 +1160,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* EMRS dll's enabled */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ /* fixme hard code AL additive latency */ write32(BAR+DCALADDR, 0x0b940001); @@ -1188,7 +1188,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* CAS Latency 2.5 */ mode_reg = 0x016a0000; } - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1200,7 +1200,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) do_delay(); do_delay(); do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1210,17 +1210,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Do 2 refreshes */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) @@ -1228,33 +1228,33 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } do_delay(); /* for good luck do 6 more */ - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); /* MRS reset dll's normal */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1279,7 +1279,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+DCALCSR, 0x0000000f); /* DDR1 This is test code to copy some codes in the factory setup */ - + write32(BAR, 0x00100000); if ((drc & 3) == 2) { /* DDR2 */ @@ -1292,9 +1292,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* receive enable calibration */ set_receive_enable(ctrl); - + /* DQS */ - pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 ); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 ); for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) { write32(cnt, dqs_data[i]); } @@ -1303,7 +1303,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Enable refresh */ /* 0x7c DRC */ data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ @@ -1311,7 +1311,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(i=0;i<64;i+=4) { write32(BAR+DCALDATA+i, 0x00000000); } - + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1331,22 +1331,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) break; } print_debug("Done\n"); - + /* Set initialization complete */ /* 0x7c DRC */ drc |= (1 << 29); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); /* Set the ecc mode */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc); /* Enable memory scrubbing */ - /* 0x52 MCHSCRB */ + /* 0x52 MCHSCRB */ data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), MCHSCRB); data16 &= ~0x0f; data16 |= ((2 << 2) | (2 << 0)); - pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16); + pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16); /* The memory is now setup, use it */ cache_lbmem(MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/e7525/memory_initialized.c b/src/northbridge/intel/e7525/memory_initialized.c index 6eb31a8ca3..69bfdf32dd 100644 --- a/src/northbridge/intel/e7525/memory_initialized.c +++ b/src/northbridge/intel/e7525/memory_initialized.c @@ -6,4 +6,4 @@ static inline int memory_initialized(void) uint32_t drc; drc = pci_read_config32(NB_DEV, DRC); return (drc & (1<<29)); -} +} diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 02bf119b96..559dc15b8b 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -16,7 +16,7 @@ static unsigned int max_bus; -static void ram_resource(device_t dev, unsigned long index, +static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { struct resource *resource; @@ -195,7 +195,7 @@ static void mc_set_resources(device_t dev) static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/northbridge/intel/e7525/pciexp_porta.c b/src/northbridge/intel/e7525/pciexp_porta.c index 3efc378ce0..4bae287df4 100644 --- a/src/northbridge/intel/e7525/pciexp_porta.c +++ b/src/northbridge/intel/e7525/pciexp_porta.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA, }; - + diff --git a/src/northbridge/intel/e7525/pciexp_porta1.c b/src/northbridge/intel/e7525/pciexp_porta1.c index 4f4204b7ad..b54ee8add6 100644 --- a/src/northbridge/intel/e7525/pciexp_porta1.c +++ b/src/northbridge/intel/e7525/pciexp_porta1.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA1, }; - + diff --git a/src/northbridge/intel/e7525/pciexp_portb.c b/src/northbridge/intel/e7525/pciexp_portb.c index faf34dcfae..7b78b42e07 100644 --- a/src/northbridge/intel/e7525/pciexp_portb.c +++ b/src/northbridge/intel/e7525/pciexp_portb.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PB, }; - + diff --git a/src/northbridge/intel/e7525/pciexp_portc.c b/src/northbridge/intel/e7525/pciexp_portc.c index d7d75a2f9c..da6eaf70de 100644 --- a/src/northbridge/intel/e7525/pciexp_portc.c +++ b/src/northbridge/intel/e7525/pciexp_portc.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PC, }; - + diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index 0d18022020..be44434bf5 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -33,13 +33,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl) /* CKDIS 0x8c disable clocks */ PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - /* 0x9c Device present and extended RAM control + /* 0x9c Device present and extended RAM control * DEVPRES is very touchy, hard code the initialization * of PCI-E ports here. */ PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG, - /* 0xc8 Remap RAM base and limit off */ + /* 0xc8 Remap RAM base and limit off */ PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000, /* ??? */ @@ -57,7 +57,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG, /* 0x14 */ - PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, + PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, }; int i; int max; @@ -122,7 +122,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - + low = spd_read_byte(device, 6); /* (low byte) */ if (low < 0) goto hw_err; value = value | (low & 0xff); @@ -169,7 +169,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask) { int i; int cum; - + for(i = cum = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; if (dimm_mask & (1 << i)) { @@ -233,7 +233,7 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) } -static int spd_set_row_attributes(const struct mem_controller *ctrl, +static int spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) { @@ -264,22 +264,22 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, reg += log2(value & 0xff); /* Get the device width and convert it to a power of two */ - value = spd_read_byte(ctrl->channel0[cnt], 13); + value = spd_read_byte(ctrl->channel0[cnt], 13); if (value < 0) goto hw_err; value = log2(value & 0xff); reg += value; if(reg < 27) goto hw_err; reg -= 27; reg += (value << 2); - + dra += reg << (cnt*8); value = spd_read_byte(ctrl->channel0[cnt], 5); if (value & 2) - dra += reg << ((cnt*8)+4); + dra += reg << ((cnt*8)+4); } /* 0x70 DRA */ - pci_write_config32(ctrl->f0, DRA, dra); + pci_write_config32(ctrl->f0, DRA, dra); goto out; val_err: @@ -293,7 +293,7 @@ hw_err: } -static int spd_set_drt_attributes(const struct mem_controller *ctrl, +static int spd_set_drt_attributes(const struct mem_controller *ctrl, long dimm_mask, uint32_t drc) { int value; @@ -305,23 +305,23 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, int latency; uint32_t index = 0; uint32_t index2 = 0; - static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; + static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; static const int latency_indicies[] = { 26, 23, 9 }; /* 0x78 DRT */ drt = pci_read_config32(ctrl->f0, DRT); drt &= 3; /* save bits 1:0 */ - + for(first_dimm = 0; first_dimm < 4; first_dimm++) { - if (dimm_mask & (1 << first_dimm)) + if (dimm_mask & (1 << first_dimm)) break; } - + /* get dimm type */ value = spd_read_byte(ctrl->channel0[first_dimm], 2); if(value == 8) { drt |= (3<<5); /* back to bark write turn around & cycle add */ - } + } drt |= (3<<18); /* Trasmax */ @@ -332,22 +332,22 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */ /* Compute the lowest cas latency supported */ latency = log2(reg) -2; - + /* Loop through and find a fast clock with a low latency */ for(index = 0; index < 3; index++, latency++) { if ((latency < 2) || (latency > 4) || (!(reg & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[cnt], + value = spd_read_byte(ctrl->channel0[cnt], latency_indicies[index]); - + if(value <= cycle_time[drc&3]) { if( latency > cas_latency) { cas_latency = latency; } break; - } + } } } index = (cas_latency-2); @@ -401,7 +401,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x03c) { drt |= (0<<10); @@ -411,7 +411,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, /* Tdal Write auto precharge recovery delay */ drt |= (1<<12); - + /* Trc TRS min */ if((index2&0x0ff00)<=0x03700) drt |= (0<<14); @@ -419,9 +419,9 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, drt |= (1<<14); else drt |= (2<<14); /* spd 41 */ - + drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0140000) { drt |= (0<<20); @@ -432,7 +432,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (3<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -446,14 +446,14 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else if(value <= 0x60) { /* 167 Mhz */ /* according to new documentation CAS latency is 00 - * for bits 3:2 for all 167 Mhz + * for bits 3:2 for all 167 Mhz drt |= ((index&3)<<2); */ /* set CAS latency */ if((index&0x0ff00)<=0x03000) { drt |= (1<<8); /* Trp RAS Precharg */ } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x030) { drt |= (0<<10); @@ -462,13 +462,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (2<<12); - + drt |= (2<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (2<<16); /* Twr not defined for DDR docs say 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0180000) { drt |= (0<<20); @@ -477,7 +477,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x0480000) { drt |= (0<<22); @@ -505,13 +505,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); - + drt |= (1<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (1<<16); /* Twr not defined for DDR docs say 1 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x01e0000) { drt |= (0<<20); @@ -520,7 +520,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -529,13 +529,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<22); } - + /* Based on CAS latency */ if(index&7) drt |= (0x099<<24); else drt |= (0x055<<24); - + } else { die("Invalid SPD 9 bus speed.\n"); @@ -547,7 +547,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, return(cas_latency); } -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, +static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, long dimm_mask) { int value; @@ -558,12 +558,12 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, unsigned char dram_type = 0xff; unsigned char ecc = 0xff; unsigned char rate = 62; - static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; + static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; static const unsigned char drc_rates[5] = {0,15,7,62,3}; static const unsigned char fsb_conversion[4] = {3,1,3,2}; /* 0x7c DRC */ - drc = pci_read_config32(ctrl->f0, DRC); + drc = pci_read_config32(ctrl->f0, DRC); for(cnt=0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; @@ -578,7 +578,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if (ecc == 1) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else if ( reg == 7 ) { if ( ecc == 0xff) { ecc = 1; @@ -586,7 +586,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if ( ecc > 1 ) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else { die("ERROR - RAM not DDR\n"); } @@ -650,7 +650,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, drc |= (fsb_conversion[value] << 2); drc &= ~(3 << 0); /* set the dram type */ drc |= (dram_type << 0); - + goto out; val_err: @@ -662,7 +662,7 @@ hw_err: return drc; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { long dimm_mask; @@ -681,7 +681,7 @@ static void do_delay(void) unsigned char b; for(i=0;i<16;i++) b=inb(0x80); -} +} #define TIMEOUT_LOOPS 300000 @@ -695,7 +695,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) unsigned int dimm,i; unsigned int data32; unsigned int t4; - + /* Set up northbridge values */ /* ODT enable */ pci_write_config32(ctrl->f0, 0x88, 0xf0000180); @@ -712,10 +712,10 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) for(i=0;i<1;i++) { if((t4&0x0f) == 1) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00000010; /* EEES */ + data32 = 0x00000010; /* EEES */ break; } - if ( ((t4>>16)&0x0f) == 0 ) { + if ( ((t4>>16)&0x0f) == 0 ) { data32 = 0x00003132; /* EESS */ break; } @@ -728,7 +728,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) } if((t4&0x0f) == 2) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00003132; /* EEED */ + data32 = 0x00003132; /* EEED */ break; } if ( ((t4>>8)&0x0f) == 2 ) { @@ -755,14 +755,14 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, 0x83000003 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) break; } } -} +} static void set_receive_enable(const struct mem_controller *ctrl) { unsigned int i; @@ -770,7 +770,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) uint32_t recena=0; uint32_t recenb=0; - { + { unsigned int dimm; unsigned int edge; int32_t data32; @@ -788,7 +788,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) if(!(dimm&1)) { write32(BAR+DCALDATA+(17*4), 0x04020000); write32(BAR+DCALCSR, 0x83800004 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) @@ -796,7 +796,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) } if(i>=1000) continue; - + dcal_data32_0 = read32(BAR+DCALDATA + 0); dcal_data32_1 = read32(BAR+DCALDATA + 4); dcal_data32_2 = read32(BAR+DCALDATA + 8); @@ -883,7 +883,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) data32++; } /* test for frame edge cross overs */ - if((edge == 1) && (data32 > 12) && + if((edge == 1) && (data32 > 12) && (((recen+16)-data32) < 3)) { data32 = 0; cnt += 2; @@ -1034,15 +1034,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* FSB 200 DIMM 400 */ {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}}, }; - + static const uint32_t dqs_data[] = { - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); @@ -1071,24 +1071,24 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* 0x7c DRC */ pci_write_config32(ctrl->f0, DRC, data32); - + /* turn the clocks on */ /* 0x8c CKDIS */ pci_write_config16(ctrl->f0, CKDIS, 0x0000); - + /* 0x9a DDRCSR Take subsystem out of idle */ data16 = pci_read_config16(ctrl->f0, DDRCSR); data16 &= ~(7 << 12); data16 |= (3 << 12); /* use dual channel lock step */ pci_write_config16(ctrl->f0, DDRCSR, data16); - + /* program row size DRB */ spd_set_ram_size(ctrl, mask); /* program page size DRA */ spd_set_row_attributes(ctrl, mask); - /* program DRT timing values */ + /* program DRT timing values */ cas_latency = spd_set_drt_attributes(ctrl, mask, drc); for(i=0;i<8;i++) { /* loop throught each dimm to test for row */ @@ -1097,7 +1097,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); /* Apply NOP */ do_delay(); - + write32(BAR + 0x100, (0x03000000 | (i<<20))); write32(BAR+0x100, (0x83000000 | (i<<20))); @@ -1107,12 +1107,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 = read32(BAR+DCALCSR); } - + /* Apply NOP */ do_delay(); - for(cs=0;cs<8;cs++) { - write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); + for(cs=0;cs<8;cs++) { + write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); @@ -1120,7 +1120,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharg all banks */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1130,10 +1130,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* EMRS dll's enabled */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ /* fixme hard code AL additive latency */ write32(BAR+DCALADDR, 0x0b940001); @@ -1158,7 +1158,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* CAS Latency 2.5 */ mode_reg = 0x016a0000; } - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1170,7 +1170,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) do_delay(); do_delay(); do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1180,17 +1180,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Do 2 refreshes */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) @@ -1198,33 +1198,33 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } do_delay(); /* for good luck do 6 more */ - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); /* MRS reset dll's normal */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1249,7 +1249,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+DCALCSR, 0x0000000f); /* DDR1 This is test code to copy some codes in the factory setup */ - + write32(BAR, 0x00100000); if ((drc & 3) == 2) { /* DDR2 */ @@ -1259,9 +1259,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* receive enable calibration */ set_receive_enable(ctrl); - + /* DQS */ - pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); + pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) { write32(cnt, dqs_data[i]); } @@ -1270,7 +1270,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Enable refresh */ /* 0x7c DRC */ data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ @@ -1278,7 +1278,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(i=0;i<64;i+=4) { write32(BAR+DCALDATA+i, 0x00000000); } - + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1298,22 +1298,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) break; } print_debug("Done\n"); - + /* Set initialization complete */ /* 0x7c DRC */ drc |= (1 << 29); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); /* Set the ecc mode */ - pci_write_config32(ctrl->f0, DRC, drc); + pci_write_config32(ctrl->f0, DRC, drc); /* Enable memory scrubbing */ - /* 0x52 MCHSCRB */ + /* 0x52 MCHSCRB */ data16 = pci_read_config16(ctrl->f0, MCHSCRB); data16 &= ~0x0f; data16 |= ((2 << 2) | (2 << 0)); - pci_write_config16(ctrl->f0, MCHSCRB, data16); + pci_write_config16(ctrl->f0, MCHSCRB, data16); /* The memory is now setup, use it */ cache_lbmem(MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index d6400d5859..42f624aaf7 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -59,7 +59,7 @@ static void pcie_bus_enable_resources(struct device *dev) if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n"); pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8); - + dev->command |= PCI_COMMAND_IO; dev->command |= PCI_COMMAND_MEMORY; } diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 5a4a328e44..7aeef29c84 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -34,7 +34,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000, PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a, - PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0, + PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0, }; int i; int max; @@ -89,7 +89,7 @@ static struct dimm_size spd_get_dimm_size(u16 device) if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - + low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); if (low < 0) goto hw_err; value = value | (low & 0xff); @@ -143,7 +143,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask) { int i; int cum; - + for (i = cum = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; if (dimm_mask & (1 << i)) { @@ -212,7 +212,7 @@ static u8 spd_detect_dimms(const struct mem_controller *ctrl) } -static int spd_set_row_attributes(const struct mem_controller *ctrl, +static int spd_set_row_attributes(const struct mem_controller *ctrl, u8 dimm_mask) { int value; @@ -258,7 +258,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, /* set device width (x8) */ dra |= (1 << 4); dra |= (1 << 10); - + /* set device type (registered) */ dra |= (1 << 14); @@ -278,7 +278,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, } -static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, +static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, u8 dimm_mask, u32 drc) { int i; @@ -409,7 +409,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, return val; } -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, +static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, u8 dimm_mask) { int value; @@ -486,7 +486,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, return drc; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { u8 dimm_mask; int i; @@ -506,7 +506,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) u32 dimm,i; u32 data32; u32 t4; - + /* Set up northbridge values */ /* ODT enable */ pci_write_config32(ctrl->f0, SDRC, 0xa0002c30); @@ -581,17 +581,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 = data32 | (3 << 5); /* temp turn off ODT */ /* Set DRAM controller mode */ pci_write_config32(ctrl->f0, DRC, data32); - + /* Turn the clocks on */ pci_write_config16(ctrl->f0, CKDIS, 0x0000); - + /* Program row size */ spd_set_ram_size(ctrl, mask); - + /* Program row attributes */ spd_set_row_attributes(ctrl, mask); - /* Program timing values */ + /* Program timing values */ mode_reg = spd_set_drt_attributes(ctrl, mask, drc); dump_dcal_regs(); @@ -608,14 +608,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Apply NOP */ udelay(16); for (cs = 0; cs < 2; cs++) { print_debug("NOP CS"); print_debug_hex8(cs); print_debug("\n"); - write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); + write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); @@ -623,7 +623,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharge all banks */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("Precharge CS"); print_debug_hex8(cs); print_debug("\n"); @@ -633,10 +633,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* EMRS: Enable DLLs, set OCD calibration mode to default */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("EMRS CS"); print_debug_hex8(cs); print_debug("\n"); @@ -648,7 +648,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* MRS: Reset DLLs */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("MRS CS"); print_debug_hex8(cs); print_debug("\n"); @@ -661,7 +661,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharge all banks */ udelay(48); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("Precharge CS"); print_debug_hex8(cs); print_debug("\n"); @@ -671,11 +671,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Do 2 refreshes */ for (i = 0; i < 2; i++) { udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("Refresh CS"); print_debug_hex8(cs); print_debug("\n"); @@ -688,7 +688,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* MRS: Set DLLs to normal */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("MRS CS"); print_debug_hex8(cs); print_debug("\n"); @@ -734,7 +734,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + dump_dcal_regs(); /* Adjust RCOMP */ @@ -746,11 +746,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) dump_dcal_regs(); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); write32(BAR+DCALCSR, 0x0008000f); /* Clear memory and init ECC */ - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { if (!(mask & (1<<cs))) continue; print_debug("clear memory CS"); @@ -779,10 +779,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) drc |= (1 << 29); drc |= (3 << 30); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); /* Set the ECC mode */ - pci_write_config32(ctrl->f0, DRC, drc); + pci_write_config32(ctrl->f0, DRC, drc); /* The memory is now set up--use it */ cache_lbmem(MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 4de84d3472..99f043f778 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -30,7 +30,7 @@ config SDRAMPWR_4DIMM This option affects how the SDRAMC register is programmed. Memory clock signals will not be routed properly if this option is set wrong. - + If your board has 4 DIMM slots, you must use select this option, in your Kconfig file of the board. On boards with 3 DIMM slots, do _not_ select this option. diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index b437755213..34f4fd4fed 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -8,8 +8,8 @@ static void dump_spd_registers(void) device = DIMM_SPD_BASE + i; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 97311c5fdf..2edbe8ba3f 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -72,10 +72,10 @@ #define AGPCTRL 0xb0 /* AGP Control Register (0x00000000) */ #define APSIZE 0xb4 /* Aperture Size Control Register (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table (0x00000000) */ - + #define MBFS 0xca /* Memory Buffer Frequency Select (0x000000). */ #define BSPAD 0xd0 /* BIOS Scratch Pad (0x000..000). */ -#define BSPAD0 0xd0 /* These are free for our use. */ +#define BSPAD0 0xd0 /* These are free for our use. */ #define BSPAD1 0xd1 #define BSPAD2 0xd2 #define BSPAD3 0xd3 diff --git a/src/northbridge/intel/i440lx/Makefile.inc b/src/northbridge/intel/i440lx/Makefile.inc index f4ef7d49c2..c6b480940f 100644 --- a/src/northbridge/intel/i440lx/Makefile.inc +++ b/src/northbridge/intel/i440lx/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.o +driver-y += northbridge.o diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index ebe38afd51..7ebc002c72 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -33,7 +33,7 @@ #include "northbridge.h" #include "i440lx.h" -/* This code is mostly same as 440BX created by Uwe Hermann, +/* This code is mostly same as 440BX created by Uwe Hermann, * i done only very minor changes like renamed functions to 440lx etc * Maciej */ diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c index 61ddde98ca..d8cebb2808 100644 --- a/src/northbridge/intel/i440lx/raminit.c +++ b/src/northbridge/intel/i440lx/raminit.c @@ -61,14 +61,14 @@ static const long register_values[] = { // 0x04 == bit 10 // BASE is 0x8A but we dont want bit 9 or 10 have ENABLED so 0x8C PACCFG + 1, 0x38, 0x8c, - + DBC, 0x00, 0xC3, DRT, 0x00, 0xFF, DRT+1, 0x00, 0xFF, DRAMC, 0x00, 0x00, /* disable refresh for now. */ - DRAMT, 0x00, 0x00, + DRAMT, 0x00, 0x00, PAM0, 0x00, 0x30, // everything is a mem PAM1, 0x00, 0x33, @@ -109,7 +109,7 @@ static void do_ram_command(u32 command) u32 addr, addr_offset; /* Configure the RAM command. */ - reg16 = pci_read_config16(NB, DRAMXC); + reg16 = pci_read_config16(NB, DRAMXC); reg16 &= 0xff1f; /* Clear bits 7-5. */ reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */ pci_write_config16(NB, DRAMXC, reg16); @@ -127,7 +127,7 @@ static void do_ram_command(u32 command) addr_offset = 0; caslatency = 3; /* TODO: Dynamically get CAS latency later. */ - /* before translation it is + /* before translation it is * * M[02:00] Burst Length * M[03:03] Burst Type @@ -153,7 +153,7 @@ static void do_ram_command(u32 command) * must be left shifted by 3 * so possible formula is (caslatency <<4)|(burst_type << 1)|(burst length) * then << 3 shift to compensate shift in Memory Controller - */ + */ if (command == RAM_COMMAND_MRS) { if (caslatency == 3) addr_offset = 0x1d0; @@ -194,7 +194,7 @@ static void spd_enable_refresh(void) /* this chipset offer only two choices regarding refresh * refresh disabled, or refresh normal */ - + pci_write_config8(NB, DRAMC, reg | 0x01); reg = pci_read_config8(NB, DRAMC); @@ -216,10 +216,10 @@ static void northbridge_init(void) pci_write_config32(NB, APBASE, reg32); #ifdef DEBUG_RAM_SETUP - /* - * apbase dont get set still, no idea what i have doing wrong yet, + /* + * apbase dont get set still, no idea what i have doing wrong yet, * i am almost sure that somehow i set it by mistake once, but can't - * repeat that. + * repeat that. */ reg32 = pci_read_config32(NB, APBASE); PRINT_DEBUG("APBASE "); @@ -238,11 +238,11 @@ static void sdram_set_registers(void) int i, max; /* nice banner with FSB shown? do we have - * any standart policy about such things? + * any standart policy about such things? */ #if 0 uint16_t reg16; - reg16 = pci_read_config16(NB, PACCFG); + reg16 = pci_read_config16(NB, PACCFG); printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\n", (reg16 & 0x4000) ? '0' : '6'); #endif @@ -261,8 +261,8 @@ static void sdram_set_registers(void) reg |= register_values[i + 2] & ~(register_values[i + 1]); pci_write_config8(NB, register_values[i], reg); - /* - * i am not sure if that is needed, but was usefull + /* + * i am not sure if that is needed, but was usefull * for me to confirm what got written */ #ifdef DEBUG_RAM_SETUP @@ -282,7 +282,7 @@ static void sdram_set_registers(void) #endif } - PRINT_DEBUG("Northbridge atexit sdram set registers\n"); + PRINT_DEBUG("Northbridge atexit sdram set registers\n"); DUMPNORTH(); } @@ -293,9 +293,9 @@ static void sdram_set_spd_registers(void) u16 memsize = 0; for (i = 0; i < DIMM_SOCKETS; i++) { - uint16_t ds = 0; // dimm size + uint16_t ds = 0; // dimm size int j; - /* this code skips second bank on each socket (no idea how to fix it now) + /* this code skips second bank on each socket (no idea how to fix it now) */ PRINT_DEBUG("DIMM"); @@ -321,8 +321,8 @@ static void sdram_set_spd_registers(void) /* This is more or less crude hack - * allowing to run this target under qemu (even if that is not really - * same hardware emulated), + * allowing to run this target under qemu (even if that is not really + * same hardware emulated), * probably some kconfig expert option should be added to enable/disable * this nicelly */ @@ -333,10 +333,10 @@ static void sdram_set_spd_registers(void) // todo: support for bank with not equal sizes as per jedec standart? - + /* * because density is reported in units of 4Mbyte - * and rows in device are just value, + * and rows in device are just value, * and for setting registers we need value in 8Mbyte units */ @@ -348,7 +348,7 @@ static void sdram_set_spd_registers(void) pci_write_config8(NB, DRB + (2*i), memsize); pci_write_config8(NB, DRB + (2*i) + 1, memsize); if (ds > 0) { - /* i have no idea why pci_read_config16 not work for + /* i have no idea why pci_read_config16 not work for * me correctly here */ ds = pci_read_config8(NB, DRT+1); @@ -364,9 +364,9 @@ static void sdram_set_spd_registers(void) PRINT_DEBUG_HEX16(ds); PRINT_DEBUG("\n"); - /* + /* * modify DRT register if current row isn't empty - * code assume its SDRAM plugged (should check if its sdram or EDO, + * code assume its SDRAM plugged (should check if its sdram or EDO, * edo would have 0x00 as constand instead 0x10 for SDRAM * also this code is buggy because ignores second row of each dimm socket */ @@ -400,7 +400,7 @@ static void sdram_set_spd_registers(void) pci_write_config8(NB, DRAMC, 0x00); /* Cas latency 3, and other shouldbe properly from spd too */ - pci_write_config8(NB, DRAMT, 0xAC); + pci_write_config8(NB, DRAMT, 0xAC); /* TODO? */ pci_write_config8(NB, PCI_LATENCY_TIMER, 0x40); diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c index 87b039f5f5..5bddbb60a3 100644 --- a/src/northbridge/intel/i82810/debug.c +++ b/src/northbridge/intel/i82810/debug.c @@ -8,8 +8,8 @@ static void dump_spd_registers(void) device = DIMM_SPD_BASE + i; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index fbb64f6088..81148e313d 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -312,7 +312,7 @@ static void set_dram_buffer_strength(void) SPD_NUM_DIMM_BANKS) > 1; d1.ss = !d1.ds; } - + buff_sc = 0; /* Tame the beast... */ @@ -350,7 +350,7 @@ static void set_dram_buffer_strength(void) buff_sc |= 1 << 14; if (!d0.size && d1.size) buff_sc |= 1 << 15; - + print_debug("BUFF_SC calculated to 0x"); print_debug_hex16(buff_sc); print_debug("\n"); @@ -371,7 +371,7 @@ static void sdram_set_registers(void) /* Ideally, this should be R/W for as many ranges as possible. */ pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff); - + /* Set size for onboard-VGA framebuffer. */ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM); reg8 &= 0x3f; /* Disable graphics (for now). */ diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h index 5a06dd171d..8c558a5699 100644 --- a/src/northbridge/intel/i82810/raminit.h +++ b/src/northbridge/intel/i82810/raminit.h @@ -27,7 +27,7 @@ /* DIMM0 is at 0x50, DIMM1 is at 0x51. */ #define DIMM_SPD_BASE 0x50 -/* The following table has been bumped over to this header to avoid clutter in +/* The following table has been bumped over to this header to avoid clutter in * raminit.c. It's used to translate the value read from SPD Byte 31 to a value * the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most * northbridges have some sort of simple calculation that can be done for this, @@ -38,7 +38,7 @@ /* TODO: Find a better way of doing this. */ static const uint8_t translate_spd_to_i82810[] = { - /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB + /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB * side can't be either, at least for now. */ /* TODO: For above case, only use the other side if > 4MB, and get some diff --git a/src/northbridge/intel/i82830/i82830_smihandler.c b/src/northbridge/intel/i82830/i82830_smihandler.c index 515be54acc..c9c7bcb27f 100644 --- a/src/northbridge/intel/i82830/i82830_smihandler.c +++ b/src/northbridge/intel/i82830/i82830_smihandler.c @@ -194,10 +194,10 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i+=16; continue; } - + mbi_header = (mbi_header_t *)&mbi[i]; len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + mbi_header->name_len, 16); - + if (obj_header->objnum == count) { #ifdef DEBUG_SMI_I82830 if (mbi_header->name_len == 0xff) { @@ -224,7 +224,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i += len; count++; } - if (obj_header->banner.retsts == MSH_IF_NOT_FOUND) + if (obj_header->banner.retsts == MSH_IF_NOT_FOUND) printk(BIOS_DEBUG, "| |- MBI object #%d not found.\n", obj_header->objnum); break; } @@ -251,10 +251,10 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i+=16; continue; } - + mbi_header = (mbi_header_t *)&mbi[i]; len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + mbi_header->name_len, 16); - + if (getobj->objnum == count) { printk(BIOS_DEBUG, "| |- len = %x\n", len); memcpy((void *)(getobj->buffer + OBJ_OFFSET), @@ -270,7 +270,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i += len; count++; } - if (getobj->banner.retsts == MSH_IF_NOT_FOUND) + if (getobj->banner.retsts == MSH_IF_NOT_FOUND) printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum); break; } diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c index 66b591b548..21c677960e 100644 --- a/src/northbridge/intel/i82830/vga.c +++ b/src/northbridge/intel/i82830/vga.c @@ -68,7 +68,7 @@ static void vga_init(device_t dev) #define PIPE_A_TV (1 << 3) #define PIPE_B_CRT (1 << 8) #define PIPE_B_TV (1 << 10) - printk(BIOS_DEBUG, "Enabling TV-Out\n"); + printk(BIOS_DEBUG, "Enabling TV-Out\n"); void runInt10(void); M.x86.R_AX = 0x5f64; M.x86.R_BX = 0x0001; // Set Display Device, force execution diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c index c353776c12..2f7d5342a1 100644 --- a/src/northbridge/intel/i855/debug.c +++ b/src/northbridge/intel/i855/debug.c @@ -31,8 +31,8 @@ static void print_debug_pci_dev(unsigned dev) static inline void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -51,7 +51,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -70,8 +70,8 @@ static void dump_pci_device(unsigned dev) static inline void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -93,8 +93,8 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -130,7 +130,7 @@ static inline void dump_smbus_registers(void) print_debug("smbus: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { - int status; + int status; unsigned char byte; if ((j & 0xf) == 0) { print_debug("\n"); @@ -147,5 +147,5 @@ static inline void dump_smbus_registers(void) print_debug_char(' '); } print_debug("\n"); - } + } } diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 03bf3a93b6..3495fb6cfb 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -79,15 +79,15 @@ static void pci_domain_set_resources(device_t dev) { device_t mc_dev; uint32_t pci_tolm; - + printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device); - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev->link[0].children->sibling; printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor); printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device); - + if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. * This is all computed in kilobytes and converted to/from @@ -117,7 +117,7 @@ static void pci_domain_set_resources(device_t dev) /* Write the ram configuration registers, * preserving the reserved bits. */ - + /* Report the memory regions */ printk(BIOS_DEBUG, "tomk = %ld\n", tomk); printk(BIOS_DEBUG, "tolmk = %ld\n", tolmk); @@ -143,7 +143,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 5d71a27ca1..386eda10bb 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -17,7 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include <sdram_mode.h> #include <delay.h> @@ -28,7 +28,7 @@ * Set only what I need until it works, then make it figure things out on boot * assumes only one dimm is populated */ - + static void sdram_set_registers(const struct mem_controller *ctrl) { /* @@ -40,7 +40,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) static void spd_set_row_attributes(const struct mem_controller *ctrl) { uint16_t dra_reg; - + dra_reg = 0x7733; pci_write_config16(ctrl->d0, 0x50, dra_reg); } @@ -48,7 +48,7 @@ static void spd_set_row_attributes(const struct mem_controller *ctrl) static void spd_set_dram_controller_mode(const struct mem_controller *ctrl) { uint32_t drc_reg; - + /* drc_reg = 0x00009101; */ drc_reg = 0x00009901; pci_write_config32(ctrl->d0, 0x70, drc_reg); @@ -57,7 +57,7 @@ static void spd_set_dram_controller_mode(const struct mem_controller *ctrl) static void spd_set_dram_timing(const struct mem_controller *ctrl) { uint32_t drt_reg; - + drt_reg = 0x2a004405; pci_write_config32(ctrl->d0, 0x60, drt_reg); } @@ -73,7 +73,7 @@ static void spd_set_dram_size(const struct mem_controller *ctrl) static void spd_set_dram_pwr_management(const struct mem_controller *ctrl) { uint32_t pwrmg_reg; - + pwrmg_reg = 0x10f10430; pci_write_config32(ctrl->d0, 0x68, pwrmg_reg); } @@ -97,31 +97,31 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl) pci_write_config32(PCI_DEV(0, 0, 0), 0x2c, 0x35808086); pci_write_config32(PCI_DEV(0, 0, 0), 0x48, 0xfec10000); pci_write_config32(PCI_DEV(0, 0, 0), 0x50, 0x00440100); - + pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x11111000); - + pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0002); */ pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0044); /* pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0000); */ - pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x33333000); + pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x33333000); pci_write_config32(PCI_DEV(0, 0, 0), 0x5c, 0x33333333); /* pci_write_config32(PCI_DEV(0, 0, 0), 0x60, 0x0000390a); pci_write_config32(PCI_DEV(0, 0, 0), 0x74, 0x02006056); pci_write_config32(PCI_DEV(0, 0, 0), 0x78, 0x00800001); */ - pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x00000001); - + pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x00000001); + pci_write_config32(PCI_DEV(0, 0, 0), 0xbc, 0x00001020); /* pci_write_config32(PCI_DEV(0, 0, 0), 0xfc, 0x00000109); */ /* 0:0.1 */ - pci_write_config32(ctrl->d0, 0x74, 0x00000001); + pci_write_config32(ctrl->d0, 0x74, 0x00000001); pci_write_config32(ctrl->d0, 0x78, 0x001fe974); pci_write_config32(ctrl->d0, 0x80, 0x00af0039); pci_write_config32(ctrl->d0, 0x84, 0x0000033c); @@ -133,7 +133,7 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl) pci_write_config32(ctrl->d0, 0xb8, 0x000055d4); pci_write_config32(ctrl->d0, 0xbc, 0x024acd38); pci_write_config32(ctrl->d0, 0xc0, 0x00000003); - + /* 0:0.3 */ /* pci_write_config32(PCI_DEV(0, 0, 3), 0x2c, 0x35858086); @@ -147,12 +147,12 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl) pci_write_config32(PCI_DEV(0, 0, 3), 0x7c, 0x0284007f); pci_write_config32(PCI_DEV(0, 0, 3), 0x84, 0x000000ef); */ - + /* pci_write_config16(PCI_DEV(0, 0, 3), 0xc0, 0x0200); pci_write_config16(PCI_DEV(0, 0, 3), 0xc0, 0x0400); */ - + /* pci_write_config32(PCI_DEV(0, 0, 3), 0xc4, 0x00000000); pci_write_config32(PCI_DEV(0, 0, 3), 0xd8, 0xff00c308); @@ -180,7 +180,7 @@ static void ram_command(const struct mem_controller *ctrl, uint32_t addr) { uint32_t drc_reg; - + drc_reg = pci_read_config32(ctrl->d0, 0x70); drc_reg &= ~(7 << 4); drc_reg |= (command << 4); @@ -195,12 +195,12 @@ static void ram_command_mrs(const struct mem_controller *ctrl, { uint32_t drc_reg; uint32_t adjusted_mode; - + drc_reg = pci_read_config32(ctrl->d0, 0x70); drc_reg &= ~(7 << 4); drc_reg |= (command << 4); pci_write_config8(ctrl->d0, 0x70, drc_reg); - /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */ + /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */ adjusted_mode = ((mode & 0x800) << (13 - 11)) | ((mode & 0x3ff) << (12 - 9)); print_debug("Setting mode: "); print_debug_hex32(adjusted_mode + addr); @@ -211,7 +211,7 @@ static void ram_command_mrs(const struct mem_controller *ctrl, static void set_initialize_complete(const struct mem_controller *ctrl) { uint32_t drc_reg; - + drc_reg = pci_read_config32(ctrl->d0, 0x70); drc_reg |= (1 << 29); pci_write_config32(ctrl->d0, 0x70, drc_reg); @@ -224,7 +224,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("Ram enable 1\n"); delay(); delay(); - + print_debug("Ram enable 2\n"); ram_command(ctrl, 1, 0); ram_command(ctrl, 1, rank1); @@ -242,17 +242,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, rank1); delay(); delay(); - + print_debug("Ram enable 5\n"); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, 0); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, rank1); - + print_debug("Ram enable 6\n"); ram_command(ctrl, 2, 0); ram_command(ctrl, 2, rank1); delay(); delay(); - + print_debug("Ram enable 7\n"); for(i = 0; i < 8; i++) { ram_command(ctrl, 6, 0); @@ -270,19 +270,19 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) ram_command(ctrl, 7, rank1); delay(); delay(); - + print_debug("Ram enable 9\n"); set_initialize_complete(ctrl); - + delay(); delay(); delay(); - + print_debug("After configuration:\n"); /* dump_pci_devices(); */ - + /* - print_debug("\n\n***** RAM TEST *****\n"); + print_debug("\n\n***** RAM TEST *****\n"); ram_check(0, 0xa0000); ram_check(0x100000, 0x40000000); */ diff --git a/src/northbridge/intel/i855/reset_test.c b/src/northbridge/intel/i855/reset_test.c index b48b4a3764..40f2f89973 100644 --- a/src/northbridge/intel/i855/reset_test.c +++ b/src/northbridge/intel/i855/reset_test.c @@ -28,12 +28,12 @@ static int bios_reset_detected(void) { uint32_t dword; - + dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - + if( (dword & DRC_DONE) != 0 ) { return 1; - } - + } + return 0; } diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 6002a76876..dd095ca7b3 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -26,8 +26,8 @@ static inline void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -64,8 +64,8 @@ static inline void dump_pci_device(unsigned dev) static inline void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -86,7 +86,7 @@ static inline void dump_spd_registers(void) int status = 0; int i; printk(BIOS_DEBUG, "\ndimm %02x", device); - + for(i = 0; (i < 256) ; i++) { if ((i % 16) == 0) { printk(BIOS_DEBUG, "\n%02x: ", i); @@ -94,7 +94,7 @@ static inline void dump_spd_registers(void) status = smbus_read_byte(device, i); if (status < 0) { printk(BIOS_DEBUG, "bad device: %02x\n", -status); - break; + break; } printk(BIOS_DEBUG, "%02x ", status); } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index db24c93a0d..3c54b98855 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -199,7 +199,7 @@ static int sdram_capabilities_two_dimms_per_channel(void) return (reg8 != 0); } -// TODO check if we ever need this function +// TODO check if we ever need this function #if 0 static int sdram_capabilities_MEM4G_disable(void) { diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 80dcc8d1a9..3fbc358de5 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -45,7 +45,7 @@ static void memctrl_init(device_t dev) /* vlink mirror */ vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN400_VLINK, 0); - + /* Setup Low Memory Top */ /* 0x47 == HA(32:25) */ /* 0x84/85 == HA(31:20) << 4 | DRAM Granularity */ @@ -104,7 +104,7 @@ static void memctrl_init(device_t dev) pci_write_config8(vlink_dev, 0x63, shadowreg); /* Activate VGA Frame Buffer */ - + reg8 = pci_read_config8(dev, 0xA0); reg8 |= 0x01; pci_write_config8(dev, 0xA0, reg8); @@ -268,7 +268,7 @@ static void cn400_domain_set_resources(device_t dev) (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); } assign_resources(&dev->link[0]); - + printk(BIOS_SPEW, "Leaving %s.\n", __func__); } diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c index a0b3aab1c5..7081c78744 100644 --- a/src/northbridge/via/cn400/raminit.c +++ b/src/northbridge/via/cn400/raminit.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* +/* Automatically detect and set up ddr dram on the CN400 chipset. Assumes DDR400 memory as no attempt is made to clock the chipset down if slower memory is installed. @@ -33,9 +33,9 @@ #include <cpu/x86/mtrr.h> #include "cn400.h" -static void dimm_read(unsigned long bank,unsigned long x) +static void dimm_read(unsigned long bank,unsigned long x) { - //unsigned long eax; + //unsigned long eax; volatile unsigned long y; //eax = x; y = * (volatile unsigned long *) (x+ bank) ; @@ -50,7 +50,7 @@ static void print_val(char *str, int val) } /** - * Configure the bus between the CPU and the northbridge. This might be able to + * Configure the bus between the CPU and the northbridge. This might be able to * be moved to post-ram code in the future. For the most part, these registers * should not be messed around with. These are too complex to explain short of * copying the datasheets into the comments, but most of these values are from @@ -66,27 +66,27 @@ static void c3_cpu_setup(device_t dev) /* Host bus interface registers (D0F2 0x50-0x67) */ /* Taken from CN700 and updated from running CN400 */ uint8_t reg8; - + /* Host Bus I/O Circuit (see datasheet) */ /* Host Address Pullup/down Driving */ pci_write_config8(dev, 0x70, 0x33); pci_write_config8(dev, 0x71, 0x44); pci_write_config8(dev, 0x72, 0x33); pci_write_config8(dev, 0x73, 0x44); - + /* Output Delay Stagger Control */ pci_write_config8(dev, 0x74, 0x70); - + /* AGTL+ I/O Circuit */ pci_write_config8(dev, 0x75, 0x08); - + /* AGTL+ Compensation Status */ pci_write_config8(dev, 0x76, 0x74); - + /* AGTL+ Auto Compensation Offest */ pci_write_config8(dev, 0x77, 0x00); pci_write_config8(dev, 0x78, 0x94); - + /* Request phase control */ pci_write_config8(dev, 0x50, 0xA8); @@ -94,71 +94,71 @@ static void c3_cpu_setup(device_t dev) pci_write_config8(dev, 0x60, 0x00); pci_write_config8(dev, 0x61, 0x00); pci_write_config8(dev, 0x62, 0x00); - + /* QW DRDY# Timing Control */ pci_write_config8(dev, 0x63, 0x00); pci_write_config8(dev, 0x64, 0x00); pci_write_config8(dev, 0x65, 0x00); - + /* Read Line Burst DRDY# Timing Control */ pci_write_config8(dev, 0x66, 0x00); pci_write_config8(dev, 0x67, 0x00); - + /* CPU Interface Control */ pci_write_config8(dev, 0x51, 0xFE); pci_write_config8(dev, 0x52, 0xEF); - + /* Arbitration */ pci_write_config8(dev, 0x53, 0x88); - + /* Write Policy & Reorder Latecy */ pci_write_config8(dev, 0x56, 0x00); - + /* Delivery-Trigger Control */ pci_write_config8(dev, 0x58, 0x00); - + /* IPI Control */ pci_write_config8(dev, 0x59, 0x30); - + /* CPU Misc Control */ pci_write_config8(dev, 0x5C, 0x00); - + /* Write Policy */ pci_write_config8(dev, 0x5d, 0xb2); - + /* Bandwidth Timer */ pci_write_config8(dev, 0x5e, 0x88); - + /* CPU Miscellaneous Control */ pci_write_config8(dev, 0x5f, 0xc7); - + /* CPU Miscellaneous Control */ pci_write_config8(dev, 0x55, 0x28); pci_write_config8(dev, 0x57, 0x69); - + /* CPU Host Bus Final Setup */ reg8 = pci_read_config8(dev, 0x54); reg8 |= 0x08; pci_write_config8(dev, 0x54, reg8); } - -static void ddr_ram_setup(void) + +static void ddr_ram_setup(void) { uint8_t b, c, bank, ma; uint16_t i; unsigned long bank_address; - - - print_debug("CN400 RAM init starting\n"); + + + print_debug("CN400 RAM init starting\n"); pci_write_config8(ctrl.d0f7, 0x75, 0x08); - - + + /* No Interleaving or Multi Page */ pci_write_config8(ctrl.d0f3, 0x69, 0x00); - pci_write_config8(ctrl.d0f3, 0x6b, 0x10); - + pci_write_config8(ctrl.d0f3, 0x6b, 0x10); + /* DRAM MA Map Type Device 0 Fn3 Offset 50-51 @@ -186,14 +186,14 @@ static void ddr_ram_setup(void) bank = 0x40; b = smbus_read_byte(0x50, SPD_NUM_ROWS); //print_val("\nNumber of Rows ", b); - + if( b >= 0x0d ){ // 256/512Mb - + if (b == 0x0e) bank = 0x48; else bank = 0x44; - + /* Read SPD byte 13, Primary DRAM width. */ @@ -205,7 +205,7 @@ static void ddr_ram_setup(void) /* Read SPD byte 4, Number of column addresses. - */ + */ b = smbus_read_byte(0x50, SPD_NUM_COLUMNS); //print_val("\nNo Columns ",b); if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr @@ -240,11 +240,11 @@ static void ddr_ram_setup(void) //c = 0; b = smbus_read_byte(0x50, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); if( b & 0x02 ) - { + { c = 0x40; // 2GB bank |= 0x02; } - else if( b & 0x01) + else if( b & 0x01) { c = 0x20; // 1GB if (bank == 0x48) bank |= 0x01; @@ -255,12 +255,12 @@ static void ddr_ram_setup(void) c = 0x10; // 512MB if (bank == 0x44) bank |= 0x02; } - else if( b & 0x40) - { + else if( b & 0x40) + { c = 0x08; // 256MB if (bank == 0x44) bank |= 0x01; else bank |= 0x03; - } + } else if( b & 0x20) { c = 0x04; // 128MB @@ -276,7 +276,7 @@ static void ddr_ram_setup(void) // set bank zero size pci_write_config8(ctrl.d0f3, 0x40, c); - + // SPD byte 5 # of physical banks b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS); @@ -288,7 +288,7 @@ static void ddr_ram_setup(void) } /* else { - die("Only a single DIMM is supported by EPIA-N(L)\n"); + die("Only a single DIMM is supported by EPIA-N(L)\n"); } */ // set banks 1,2,3... @@ -299,13 +299,13 @@ static void ddr_ram_setup(void) pci_write_config8(ctrl.d0f3, 0x45,c); pci_write_config8(ctrl.d0f3, 0x46,c); pci_write_config8(ctrl.d0f3, 0x47,c); - + /* Top Rank Address Mirrored to the South Bridge */ /* over the VLink */ pci_write_config8(ctrl.d0f7, 0x57, (c << 1)); ma = bank; - + /* Read SPD byte 18 CAS Latency */ b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES); /* print_debug("\nCAS Supported "); @@ -322,7 +322,7 @@ static void ddr_ram_setup(void) print_val("\nCycle time at CL X-0.5 (nS)", c); c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD); print_val("\nCycle time at CL X-1 (nS)", c); -*/ +*/ /* Scaling of Cycle Time SPD data */ /* 7 4 3 0 */ /* ns x0.1ns */ @@ -353,7 +353,7 @@ static void ddr_ram_setup(void) c = 0x10; } } - } + } /* Scale DRAM Cycle Time to tRP/tRCD */ /* 7 2 1 0 */ @@ -384,7 +384,7 @@ static void ddr_ram_setup(void) */ b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME); - + //print_val("\ntRP ",b); if ( b >= (5 * bank)) { c |= 0x03; // set tRP = 5T @@ -425,16 +425,16 @@ static void ddr_ram_setup(void) if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T - + /* Write DRAM Timing All Banks I */ pci_write_config8(ctrl.d0f3, 0x56, c); - + /* TWrite DRAM Timing All Banks II */ pci_write_config8(ctrl.d0f3, 0x57, 0x1a); - + /* DRAM arbitration timer */ pci_write_config8(ctrl.d0f3, 0x65, 0x99); - + /* DRAM Clock Device 0 Fn 3 Offset 68 */ @@ -453,7 +453,7 @@ static void ddr_ram_setup(void) /* 133MHz FSB / DDR333. See also c3_cpu_setup */ pci_write_config8(ctrl.d0f3, 0x68, 0x81); } - else + else { /* DRAM DDR Control Alert! Alert! This hardwires to */ /* 133MHz FSB / DDR266. See also c3_cpu_setup */ @@ -475,7 +475,7 @@ static void ddr_ram_setup(void) /* 4-Way Interleave With Multi-Paging (From Running System)*/ pci_write_config8(ctrl.d0f3, 0x69, c); - + /*DRAM Controller Internal Options */ pci_write_config8(ctrl.d0f3, 0x54, 0x01); @@ -484,7 +484,7 @@ static void ddr_ram_setup(void) /* DRAM Control */ pci_write_config8(ctrl.d0f3, 0x6e, 0x80); - + /* Disable refresh for now */ pci_write_config8(ctrl.d0f3, 0x6a, 0x00); @@ -497,7 +497,7 @@ static void ddr_ram_setup(void) /* DRAM Bus Turn-Around Setting */ pci_write_config8(ctrl.d0f3, 0x60, 0x01); - + /* Disable DRAM refresh */ pci_write_config8(ctrl.d0f3,0x6a,0x0); @@ -524,7 +524,7 @@ static void ddr_ram_setup(void) c = b | 0x40; pci_write_config8(ctrl.d0f3, 0xb0, c); - + /* Set RAM Decode method */ pci_write_config8(ctrl.d0f3, 0x55, 0x0a); @@ -542,14 +542,14 @@ static void ddr_ram_setup(void) CPU FSB Operating Frequency (bits 7:5) 000 : 100MHz 001 : 133MHz - 010 : 200MHz + 010 : 200MHz 011->111 : Reserved - + SDRAM BL8 (4) - + Don't change Frequency from power up defaults This seems to lockup the RAM interface - */ + */ c = pci_read_config8(ctrl.d0f2, 0x54); c |= 0x10; pci_write_config8(ctrl.d0f2, 0x54, c); @@ -566,7 +566,7 @@ static void ddr_ram_setup(void) c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_NOP; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); /* read a double word from any address of the dimm */ dimm_read(bank_address,0x1f000); @@ -576,7 +576,7 @@ static void ddr_ram_setup(void) c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_PRECHARGE; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); dimm_read(bank_address,0x1f000); @@ -584,8 +584,8 @@ static void ddr_ram_setup(void) c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_MSR_LOW; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); - /* TODO: Bank Addressing for Different Numbers of Row Addresses */ + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + /* TODO: Bank Addressing for Different Numbers of Row Addresses */ dimm_read(bank_address,0x2000); udelay(1); dimm_read(bank_address,0x800); @@ -595,14 +595,14 @@ static void ddr_ram_setup(void) c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_PRECHARGE; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); dimm_read(bank_address,0x1f200); /* CBR Cycle Enable */ c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_CBR; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); /* Read 8 times */ for (c=0;c<8;c++) { @@ -614,10 +614,10 @@ static void ddr_ram_setup(void) c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_MSR_LOW; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); -/* +/* Mode Register Definition with adjustement so that address calculation is correct - 64 bit technology, therefore a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented @@ -626,9 +626,9 @@ static void ddr_ram_setup(void) MR[9-7] CAS Latency MR[6] Burst Type 0 = sequential, 1 = interleaved MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved - MR[0-2] dont care + MR[0-2] dont care - CAS Latency + CAS Latency 000 reserved 001 reserved 010 2 @@ -657,24 +657,24 @@ static void ddr_ram_setup(void) c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_NORMAL; pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); - + bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000; } // end of for each bank - + /* Set DRAM DQS Output Control */ pci_write_config8(ctrl.d0f3, 0x79, 0x11); - + /* Set DQS A/B Input delay to defaults */ pci_write_config8(ctrl.d0f3, 0x7A, 0xA1); - pci_write_config8(ctrl.d0f3, 0x7B, 0x62); + pci_write_config8(ctrl.d0f3, 0x7B, 0x62); /* DQS Duty Cycle Control */ pci_write_config8(ctrl.d0f3, 0xED, 0x11); /* SPD byte 5 # of physical banks */ b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1; - + /* determine low bond */ if( b == 2) bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000; @@ -720,10 +720,10 @@ static void ddr_ram_setup(void) // if everything verified then found low bond break; - + } - print_val("\nLow Bond ",i); - if( i < 0xff ){ + print_val("\nLow Bond ",i); + if( i < 0xff ){ c = i++; for( ; i <0xff ; i++){ pci_write_config8(ctrl.d0f3,0x70, i); @@ -774,24 +774,24 @@ static void ddr_ram_setup(void) /* Set DQS ChA Data Output Delay to the default */ pci_write_config8(ctrl.d0f3, 0x71, 0x65); - + /* Set Ch B DQS Output Delays */ pci_write_config8(ctrl.d0f3, 0x72, 0x2a); pci_write_config8(ctrl.d0f3, 0x73, 0x29); - + pci_write_config8(ctrl.d0f3, 0x78, 0x03); /* Mystery Value */ pci_write_config8(ctrl.d0f3, 0x67, 0x50); - + /* Enable Toggle Limiting */ pci_write_config8(ctrl.d0f4, 0xA3, 0x80); - + /* DRAM refresh rate Device 0 F3 Offset 6a - TODO :: Fix for different DRAM technologies - other than 512Mb and DRAM Freq - Units of 16 DRAM clock cycles - 1. + TODO :: Fix for different DRAM technologies + other than 512Mb and DRAM Freq + Units of 16 DRAM clock cycles - 1. */ //c = pci_read_config8(ctrl.d0f3, 0x68); //c &= 0x07; @@ -799,13 +799,13 @@ static void ddr_ram_setup(void) //print_val("SPD_REFRESH = ", b); pci_write_config8(ctrl.d0f3,0x6a,0x65); - + /* SMM and APIC decoding, we do not use SMM */ b = 0x29; pci_write_config8(ctrl.d0f3, 0x86, b); /* SMM and APIC decoding mirror */ pci_write_config8(ctrl.d0f7, 0xe6, b); - + /* Open Up the Rest of the Shadow RAM */ pci_write_config8(ctrl.d0f3,0x80,0xff); pci_write_config8(ctrl.d0f3,0x81,0xff); @@ -816,10 +816,10 @@ static void ddr_ram_setup(void) pci_write_config8(ctrl.d0f7,0x76,0x50); pci_write_config8(ctrl.d0f7,0x71,0xc8); - + /* VGA device. */ pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15)); pci_write_config16(ctrl.d0f3, 0xa4, 0x0010); print_debug("CN400 raminit.c done\n"); -} +} diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c index cf9c54be23..511079b03a 100644 --- a/src/northbridge/via/cn400/vga.c +++ b/src/northbridge/via/cn400/vga.c @@ -62,7 +62,7 @@ static int via_cn400_int15_handler(struct eregs *regs) case 0x5f02: regs->eax=0x5f; regs->ebx= (regs->ebx & 0xffff0000) | 2; - regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default res=0; break; @@ -70,7 +70,7 @@ static int via_cn400_int15_handler(struct eregs *regs) regs->eax=0x860f; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); break; } diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index 63dab5b3e0..20b0afeb6e 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -51,7 +51,7 @@ static void do_ram_command(device_t dev, u8 command) } /** - * Configure the bus between the CPU and the northbridge. This might be able to + * Configure the bus between the CPU and the northbridge. This might be able to * be moved to post-ram code in the future. For the most part, these registers * should not be messed around with. These are too complex to explain short of * copying the datasheets into the comments, but most of these values are from @@ -244,7 +244,7 @@ static void sdram_set_size(const struct mem_controller *ctrl) } /** - * Set up various RAM and other control registers statically. Some of these may + * Set up various RAM and other control registers statically. Some of these may * not be needed, other should be done with SPD info, but that's a project for * the future. */ @@ -422,7 +422,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address) PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); /* Safe value for now, BL=8, WR=5, CAS=4 */ /* - * (E)MRS values are from the BPG. No direct explanation is given, but + * (E)MRS values are from the BPG. No direct explanation is given, but * they should somehow conform to the JEDEC DDR2 SDRAM Specification * (JESD79-2C). */ diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 69f188b01e..33d1fe0071 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -62,7 +62,7 @@ static int via_cn700_int15_handler(struct eregs *regs) case 0x5f02: regs->eax=0x5f; regs->ebx= (regs->ebx & 0xffff0000) | 2; - regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default res=0; break; @@ -70,7 +70,7 @@ static int via_cn700_int15_handler(struct eregs *regs) regs->eax=0x860f; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); break; } diff --git a/src/northbridge/via/cx700/cx700_early_serial.c b/src/northbridge/via/cx700/cx700_early_serial.c index a0d7301e20..3f5020f670 100644 --- a/src/northbridge/via/cx700/cx700_early_serial.c +++ b/src/northbridge/via/cx700/cx700_early_serial.c @@ -61,7 +61,7 @@ static void enable_cx700_serial(void) // turn on pnp cx700_writepnpaddr(0x87); cx700_writepnpaddr(0x87); - // now go ahead and set up com1. + // now go ahead and set up com1. // set address cx700_writepnpaddr(0x7); cx700_writepnpdata(0x2); diff --git a/src/northbridge/via/cx700/cx700_vga.c b/src/northbridge/via/cx700/cx700_vga.c index e36062d9d2..2999907616 100644 --- a/src/northbridge/via/cx700/cx700_vga.c +++ b/src/northbridge/via/cx700/cx700_vga.c @@ -120,7 +120,7 @@ static int via_cx700_int15_handler(struct eregs *regs) break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); break; } @@ -170,7 +170,7 @@ static void vga_init(device_t dev) // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); // this is how it looks: vga_enable_console(); - + /* It's not clear if these need to be programmed before or after * the VGA bios runs. Try both, clean up later */ /* Set memory rate to 200MHz */ diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 6693724ad4..5694ea31aa 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -452,7 +452,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) /* To store DDRII frequence */ pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ, val); - /* Manual reset and adjust DLL when DRAM change frequency + /* Manual reset and adjust DLL when DRAM change frequency * This is a necessary sequence. */ udelay(2000); @@ -1623,7 +1623,7 @@ static void sdram_enable(const struct mem_controller *ctrl) u8 mask; u8 val; } b0d1f0[] = { - { 0x40, 0x00, 0x8b}, + { 0x40, 0x00, 0x8b}, { 0x41, 0x80, 0x43}, { 0x42, 0x00, 0x62}, { 0x43, 0x00, 0x44}, diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 5af7836a93..8fca0eae2c 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -18,7 +18,7 @@ * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { printk(BIOS_SPEW, "VT8601 random fixup ...\n"); pci_write_config8(dev, 0x70, 0xc0); @@ -108,16 +108,16 @@ static void pci_domain_set_resources(device_t dev) for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); - /* these are ENDING addresses, not sizes. + /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. - * So we just take the max, that gives us total. + * So we just take the max, that gives us total. * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits) rambits = reg; if (reg < rambits) - printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", + printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", ramregs[i]); } printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); @@ -149,7 +149,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { @@ -182,5 +182,5 @@ static void enable_dev(struct device *dev) struct chip_operations northbridge_via_vt8601_ops = { CHIP_NAME("VIA VT8601 Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c index cb13ad4e98..2365b8d8fb 100644 --- a/src/northbridge/via/vt8601/raminit.c +++ b/src/northbridge/via/vt8601/raminit.c @@ -13,7 +13,7 @@ U.S. Government has rights to use, reproduce, and distribute this SOFTWARE. The public may copy, distribute, prepare derivative works and publicly display this SOFTWARE without charge, provided that this Notice and any statement of authorship are reproduced on all copies. -Neither the Government nor the University makes any warranty, express +Neither the Government nor the University makes any warranty, express or implied, or assumes any liability or responsibility for the use of this SOFTWARE. If SOFTWARE is modified to produce derivative works, such modified SOFTWARE should be clearly marked, so as not to confuse @@ -107,14 +107,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl) pci_write_config8(north, 0x78, 0x01); print_debug_hex8(pci_read_config8(north, 0x78)); - // dram control, see the book. + // dram control, see the book. #if DIMM_PC133 pci_write_config8(north, 0x68, 0x52); #else pci_write_config8(north, 0x68, 0x42); #endif - // dram control, see the book. + // dram control, see the book. pci_write_config8(north, 0x6B, 0x0c); // Initial setting, 256MB in each bank, will be rewritten later. @@ -125,7 +125,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) pci_write_config8(north, 0x5D, 0x80); pci_write_config8(north, 0x5E, 0xA0); pci_write_config8(north, 0x5F, 0xC0); - // It seems we have to take care of these 2 registers as if + // It seems we have to take care of these 2 registers as if // they are bank 6 and 7. pci_write_config8(north, 0x56, 0xC0); pci_write_config8(north, 0x57, 0xC0); @@ -149,7 +149,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) #endif // dram frequency select. - // enable 4K pages for 64M dram. + // enable 4K pages for 64M dram. #if DIMM_PC133 pci_write_config8(north, 0x69, 0x3c); #else @@ -181,8 +181,8 @@ static unsigned long spd_module_size(unsigned char slot) /* unsigned int module = ((0x50 + slot) << 1) + 1; */ unsigned int module = 0x50 + slot; - /* is the module there? if byte 2 is not 4, then we'll assume it - * is useless. + /* is the module there? if byte 2 is not 4, then we'll assume it + * is useless. */ print_info("Slot "); print_info_hex8(slot); @@ -292,7 +292,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config8(north, 0x6C, 0x01); print_debug("NOP\n"); /* wait 200us */ - // You need to do the memory reference. That causes the nop cycle. + // You need to do the memory reference. That causes the nop cycle. dimms_read(0); udelay(400); print_debug("PRECHARGE\n"); @@ -340,7 +340,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) dimms_read(0); udelay(200); print_debug("set ref. rate\n"); - // Set the refresh rate. + // Set the refresh rate. #if DIMM_PC133 pci_write_config8(north, 0x6A, 0x86); #else @@ -370,7 +370,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Set the MA map type. * - * 0xa should be another option, but when + * 0xa should be another option, but when * it would be used is unknown. */ diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 4920ec3973..7ba9cd6316 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -21,7 +21,7 @@ * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { device_t fb_dev; unsigned long fb; @@ -40,7 +40,7 @@ static void northbridge_init(device_t dev) pci_write_config8(dev, 0x84, 0x80); pci_write_config16(dev, 0x80, 0x610f); pci_write_config32(dev, 0x88, 0x00000002); - + fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0); if (fb_dev) { /* Fixup GART and framebuffer addresses properly. @@ -168,16 +168,16 @@ static void pci_domain_set_resources(device_t dev) for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); - /* these are ENDING addresses, not sizes. + /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. - * So we just take the max, that gives us total. + * So we just take the max, that gives us total. * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits) rambits = reg; if (reg < rambits) - printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", + printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", ramregs[i]); } printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024); @@ -210,7 +210,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c index f57127b3da..295011b785 100644 --- a/src/northbridge/via/vt8623/raminit.c +++ b/src/northbridge/via/vt8623/raminit.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* +/* Automatically detect and set up ddr dram on the CLE266 chipset. Assumes DDR memory, though chipset also supports SDRAM Assumes at least 266Mhz memory as no attempt is made to clock @@ -35,9 +35,9 @@ -void dimm_read(unsigned long bank,unsigned long x) +void dimm_read(unsigned long bank,unsigned long x) { - //unsigned long eax; + //unsigned long eax; volatile unsigned long y; //eax = x; y = * (volatile unsigned long *) (x+ bank) ; @@ -46,7 +46,7 @@ void dimm_read(unsigned long bank,unsigned long x) void -dumpnorth(device_t north) +dumpnorth(device_t north) { uint16_t r, c; for(r = 0; r < 256; r += 16) { @@ -65,7 +65,7 @@ void print_val(char *str, int val) print_debug_hex8(val); } -static void ddr_ram_setup(const struct mem_controller *ctrl) +static void ddr_ram_setup(const struct mem_controller *ctrl) { device_t north = (device_t) 0; uint8_t b, c, bank; @@ -75,7 +75,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) print_debug("vt8623 init starting\n"); north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0); north = 0; - + pci_write_config8(north,0x75,0x08); @@ -105,7 +105,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) print_val("Detecting Memory\nNumber of Banks ",b); if( b != 2 ){ // not 16 Mb type - + /* Read SPD byte 3, Number of row addresses. */ @@ -126,7 +126,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) 64/128Mb chip Read SPD byte 4, Number of column addresses. -*/ +*/ b = smbus_read_byte(0xa0,4); print_val("\nNo Columns ",b); if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr @@ -153,7 +153,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) if( b & 0x02 ) c = 0x80; // 2GB else if( b & 0x01) c = 0x40; // 1GB else if( b & 0x80) c = 0x20; // 512Mb - else if( b & 0x40) c = 0x10; // 256Mb + else if( b & 0x40) c = 0x10; // 256Mb else if( b & 0x20) c = 0x08; // 128Mb else if( b & 0x10) c = 0x04; // 64Mb else if( b & 0x08) c = 0x02; // 32Mb @@ -191,7 +191,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) print_val("\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9)); print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23)); print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25)); - + if( b & 0x10 ){ // DDR offering optional CAS 3 print_debug("\nStarting at CAS 3"); @@ -405,7 +405,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) /* MSR Enable */ pci_write_config8(north,0x6b,0x13); -/* +/* Mode Register Definition with adjustement so that address calculation is correct - 64 bit technology, therefore a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented @@ -414,9 +414,9 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) MR[9-7] CAS Latency MR[6] Burst Type 0 = sequential, 1 = interleaved MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved - MR[0-2] dont care + MR[0-2] dont care - CAS Latency + CAS Latency 000 reserved 001 reserved 010 2 @@ -498,10 +498,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) // if everything verified then found low bond break; - + } - print_val("\nLow Bond ",i); - if( i < 0xff ){ + print_val("\nLow Bond ",i); + if( i < 0xff ){ c = i++; for( ; i <0xff ; i++){ pci_write_config8(north,0x68,i ^ (i>>1) ); @@ -588,7 +588,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) pci_write_config8(north,0x71,0xc8); - + /* graphics aperture base */ diff --git a/src/northbridge/via/vt8623/vga.c b/src/northbridge/via/vt8623/vga.c index 7dbb7831b1..78ffe0aa94 100644 --- a/src/northbridge/via/vt8623/vga.c +++ b/src/northbridge/via/vt8623/vga.c @@ -57,7 +57,7 @@ static int via_vt8623_int15_handler(struct eregs *regs) case 0x5f02: regs->eax=0x5f; regs->ebx= (regs->ebx & 0xffff0000) | 2; - regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default res=0; break; @@ -65,7 +65,7 @@ static int via_vt8623_int15_handler(struct eregs *regs) regs->eax=0x860f; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); break; } @@ -122,11 +122,11 @@ static void vga_init(device_t dev) // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); // this is how it looks: vga_enable_console(); - + #ifdef MEASURE_VGA_INIT_TIME clocks2 = rdmsr(0x10); instructions = rdmsr(0xc2); - + printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo); printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo); printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo); diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index c3097cf2cb..172a8de148 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -30,8 +30,8 @@ CB_STATUS VerifyChc(void); /*=================================================================== Function : DRAMRegInitValue() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void @@ -68,7 +68,7 @@ static const u8 DramRegTbl[][3] = { // {0x79, 0x00, 0x8F }, {0x85, 0x00, 0x00}, // {0x90, 0x87, 0x78 }, - // {0x91, 0x00, 0x46 }, + // {0x91, 0x00, 0x46 }, {0x40, 0x00, 0x00}, {0, 0, 0} @@ -155,8 +155,8 @@ void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr) /*=================================================================== Function : DRAMInitializeProc() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void @@ -176,7 +176,7 @@ static BOOLEAN ChkForExistLowBank(void) Address = (u32 *) 4; *Address = EXIST_TEST_PATTERN; - // _asm {WBINVD} + // _asm {WBINVD} WaitMicroSec(100); Address = (u32 *) 8; data32 = *Address; @@ -223,7 +223,7 @@ void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr) SetEndingAddr(DramAttr, idx, 0x10); /* Assume 1G size */ if (idx < 4) /* CHA init */ InitDDR2CHA(DramAttr); // temp wjb 2007/1 only for compiling - // in the function InitDDR2,the parameter is no need + // in the function InitDDR2,the parameter is no need Status = ChkForExistLowBank(); if (Status == TRUE) { PRINT_DEBUG_MEM(" S\r"); @@ -247,8 +247,8 @@ void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr) /*=================================================================== Function : DRAMSetVRNUM() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard PhyRank: Physical Rank number @@ -285,14 +285,14 @@ void DRAMSetVRNum(DRAM_SYS_ATTR *DramAttr, u8 PhyRank /* physical rank */, /*=================================================================== Function : SetEndingAddr() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard VirRank: Virtual Rank number - Value: (value) add or subtract value to this and after banks + Value: (value) add or subtract value to this and after banks Output : Void -Purpose : Set ending address of virtual rank specified by VirRank +Purpose : Set ending address of virtual rank specified by VirRank ===================================================================*/ void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address @@ -312,8 +312,8 @@ void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address /*=================================================================== Function : InitDDR2() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void @@ -522,13 +522,13 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) /*=================================================================== Function : InitDDR2_CHB() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : Initialize DDR2 of CHB by standard sequence -Reference : +Reference : ===================================================================*/ /*// DLL: Enable Reset static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17=1, A9=1), (A11=1)(cpu address) @@ -569,7 +569,7 @@ void InitDDR2CHB( Data = 0x80; pci_write_config8(MEMCTRL, 0x54, Data); - + // step3. //disable bank paging and multi page Data=pci_read_config8(MEMCTRL, 0x69); @@ -579,18 +579,18 @@ void InitDDR2CHB( Data=pci_read_config8(MEMCTRL, 0xd3); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step 4. Initialize CHB begin Data=pci_read_config8(MEMCTRL, 0xd3); Data |= 0x40; pci_write_config8(MEMCTRL, 0xd3, Data); - + //Step 5. NOP command enable Data=pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd7, Data); - + //Step 6. issue a nop cycle,RegD3[7] 0 -> 1 Data=pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; @@ -604,7 +604,7 @@ void InitDDR2CHB( // Loop 200us for (Idx = 0; Idx < 0x10; Idx++) WaitMicroSec(10); - + // Step 8. // all banks precharge command enable Data=pci_read_config8(MEMCTRL, 0xd7); @@ -618,7 +618,7 @@ void InitDDR2CHB( pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step10. EMRS enable Data=pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; @@ -661,7 +661,7 @@ void InitDDR2CHB( Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); - //step 14. MSR DLL Reset + //step 14. MSR DLL Reset AccessAddr = CHB_MRS_DLL_150[1] >> 3; Data =(u8) (AccessAddr & 0xff); pci_write_config8(MEMCTRL, 0xd9, Data); @@ -691,7 +691,7 @@ void InitDDR2CHB( Data |= 0x10; pci_write_config8(MEMCTRL, 0xd7, Data); - + // step17. issue precharge all cycle Data=pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; @@ -718,7 +718,7 @@ void InitDDR2CHB( WaitMicroSec(200); } - + //step22. MSR enable Data=pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; @@ -730,7 +730,7 @@ void InitDDR2CHB( Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); - + //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.) //------------------------------------------------------------- //Burst Length : really offset Rx6c[1] @@ -773,7 +773,7 @@ void InitDDR2CHB( pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step 25. EMRS enable Data=pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; @@ -784,7 +784,7 @@ void InitDDR2CHB( Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step 26. OCD default AccessAddr = (CHB_OCD_Default_150ohm) >> 3; @@ -805,7 +805,7 @@ void InitDDR2CHB( pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step 25. EMRS enable Data=pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; @@ -859,12 +859,12 @@ void InitDDR2CHB( Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); - //step 31. exit the initialization mode + //step 31. exit the initialization mode Data=pci_read_config8(MEMCTRL, 0xd3); Data &= 0xBF; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step 32. Enable bank paging and multi page Data=pci_read_config8(MEMCTRL, 0x69); Data |= 0x03; @@ -874,13 +874,13 @@ void InitDDR2CHB( /*=================================================================== Function : InitDDR2CHC() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : Initialize DDR2 of CHC by standard sequence -Reference : +Reference : ===================================================================*/ // DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) static const u16 CHC_MRS_table[4] = { 0x22B, 0x23B, 0x24B, 0x25B }; // Use 1X-bandwidth MA table to init DRAM @@ -1102,7 +1102,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr) Status = VerifyChc(); if (Status != CB_SUCCESS) PRINT_DEBUG_MEM("Error!!!!CHC init error!\r"); - //step 31. exit the initialization mode + //step 31. exit the initialization mode Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0x9F; pci_write_config8(MEMCTRL, 0xdb, Data); diff --git a/src/northbridge/via/vx800/dqs_search.c b/src/northbridge/via/vx800/dqs_search.c index 785d775baf..c4971d1b17 100644 --- a/src/northbridge/via/vx800/dqs_search.c +++ b/src/northbridge/via/vx800/dqs_search.c @@ -22,8 +22,8 @@ void SetDQSOutputCHB(DRAM_SYS_ATTR * DramAttr); /*=================================================================== Function : DRAMDQSOutputSearchCHA() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void @@ -40,12 +40,12 @@ void DRAMDQSOutputSearch(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : SetDQSOutputCHA() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void -Purpose : according the frequence set CHA DQS output +Purpose : according the frequence set CHA DQS output ===================================================================*/ void SetDQSOutputCHA(DRAM_SYS_ATTR * DramAttr) { @@ -80,8 +80,8 @@ void SetDQSOutputCHA(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMDQSInputSearch() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void diff --git a/src/northbridge/via/vx800/dram_util.c b/src/northbridge/via/vx800/dram_util.c index 342a6e0454..7688ab34a8 100644 --- a/src/northbridge/via/vx800/dram_util.c +++ b/src/northbridge/via/vx800/dram_util.c @@ -30,11 +30,11 @@ void WaitMicroSec(UINTN MicroSeconds) /*=================================================================== Function : via_write_phys() -Precondition : +Precondition : Input : addr value Output : void -Purpose : +Purpose : Reference : None ===================================================================*/ @@ -47,10 +47,10 @@ void via_write_phys(volatile u32 addr, volatile u32 value) /*=================================================================== Function : via_read_phys() -Precondition : +Precondition : Input : addr -Output : u32 -Purpose : +Output : u32 +Purpose : Reference : None ===================================================================*/ @@ -63,10 +63,10 @@ u32 via_read_phys(volatile u32 addr) /*=================================================================== Function : DimmRead() -Precondition : +Precondition : Input : x -Output : u32 -Purpose : +Output : u32 +Purpose : Reference : None ===================================================================*/ @@ -80,13 +80,13 @@ u32 DimmRead(volatile u32 x) /*=================================================================== Function : DramBaseTest() -Precondition : this function used to verify memory -Input : +Precondition : this function used to verify memory +Input : BaseAdd, length, mode Output : u32 -Purpose :write into and read out to verify if dram is correct +Purpose :write into and read out to verify if dram is correct Reference : None ===================================================================*/ BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length, @@ -170,8 +170,8 @@ BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length, /*=================================================================== Function : DumpRegisters() -Precondition : -Input : +Precondition : +Input : pPCIPPI, DevNum, FuncNum @@ -209,8 +209,8 @@ void DumpRegisters(INTN DevNum, INTN FuncNum) /*=================================================================== Function : dumpnorth() -Precondition : -Input : +Precondition : +Input : pPCIPPI, Func Output : Void diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c index c6a7edda05..bdba494d85 100644 --- a/src/northbridge/via/vx800/driving_setting.c +++ b/src/northbridge/via/vx800/driving_setting.c @@ -58,7 +58,7 @@ void DRAMDriving(DRAM_SYS_ATTR * DramAttr) /* ODT Control for DQ/DQS/CKE/SCMD/DCLKO in ChA & ChB which include driving enable/range and strong/weak selection - + Processing: According to DRAM frequency to ODT control bits. Because function enable bit must be the last one to be set. So the register VIA_NB3DRAM_REGD4 and VIA_NB3DRAM_REGD3 should be @@ -125,7 +125,7 @@ static const u8 ODTLookup_TBL[ODTLookup_Tbl_count][3] = { }; #define ODT_Table_Width_DDR2 4 -// RxD6 RxD3 +// RxD6 RxD3 static const u8 ODT_Control_DDR2[ODT_Table_Width_DDR2] = { 0xFC, 0x01 }; void DrivingODT(DRAM_SYS_ATTR * DramAttr) diff --git a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c index a93c9a03c4..5e8e214d1f 100644 --- a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c +++ b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c @@ -20,7 +20,7 @@ #include "northbridge/via/vx800/driving_clk_phase_data.h" -// DQS Driving +// DQS Driving //Reg0xE0, 0xE1 // According to #Bank to set DRAM DQS Driving // #Bank 1 2 3 4 5 6 7 8 @@ -161,7 +161,7 @@ static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 } }; -/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = +/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { // (And NOT) DDR800 DDR667 DDR533 DDR400 //Reg Mask Value Value Value Value diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 8db60237b7..63755c3181 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -362,7 +362,7 @@ g) Rx73h = 32h /* decide if this is a s3 wakeup or a normal boot */ boot_mode = acpi_is_wakeup_early_via_vx800(); /*add this, to transfer "cpu restart" to "cold boot" - When this boot is not a S3 resume, and PCI registers had been written, + When this boot is not a S3 resume, and PCI registers had been written, then this must be a cpu restart(result of os reboot cmd). so we need a real "cold boot". */ if ((boot_mode != 3) && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) { @@ -371,7 +371,7 @@ g) Rx73h = 32h /*x86 cold boot I/O cmd */ enable_smbus(); - //smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this + //smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this if (bist == 0) { // CAR need mtrr untill mem is ok, so i disable this early_mtrr_init(); @@ -441,7 +441,7 @@ g) Rx73h = 32h /* For coreboot most time of S3 resume is the same as normal boot, so some memory area under 1M become dirty, - so before this happen, I need to backup the content of mem to top-mem. + so before this happen, I need to backup the content of mem to top-mem. I will reserve the 1M top-men in LBIO table in coreboot_table.c and recovery the content of 1M-mem in wakeup.c */ #if PAYLOAD_IS_SEABIOS==1 // @@ -449,7 +449,7 @@ g) Rx73h = 32h /* some idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html I want move the 1M data, I have to set some MTRRs myself. */ /* seting mtrr before back memoy save s3 resume time about 0.14 seconds */ - /*because CAR stack use cache, and here to use cache , must be careful, + /*because CAR stack use cache, and here to use cache , must be careful, 1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function) 2 before stack switch, no use variable that have value set before this 3 due to 2, take care of "cpu_reset", I directlly set it to ZERO. @@ -462,7 +462,7 @@ g) Rx73h = 32h u32 memtop4 = *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 + 0xe0000; - /* __asm__ volatile ( + /* __asm__ volatile ( "movl $0x204, %%ecx\n\t" "xorl %%edx, %%edx\n\t" "movl %0,%%eax\n\t" @@ -478,7 +478,7 @@ g) Rx73h = 32h "wrmsr\n\t" ::"g"(memtop2) ); - __asm__ volatile ( + __asm__ volatile ( "movl $0x206, %%ecx\n\t" "xorl %%edx, %%edx\n\t" "movl %0,%%eax\n\t" @@ -494,7 +494,7 @@ g) Rx73h = 32h "wrmsr\n\t" ::"g"(memtop1) ); - __asm__ volatile ( + __asm__ volatile ( "movl $0x208, %ecx\n\t" "xorl %edx, %edx\n\t" "movl $0,%eax\n\t" @@ -512,21 +512,21 @@ g) Rx73h = 32h */ // WAKE_MEM_INFO is inited in get_set_top_available_mem in tables.c // these two memcpy not not be enabled if set the MTRR around this two lines. - /*__asm__ volatile ( + /*__asm__ volatile ( "movl $0, %%esi\n\t" "movl %0, %%edi\n\t" "movl $0xa0000, %%ecx\n\t" "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop3) + "rep movsd\n\t" + ::"g"(memtop3) ); - __asm__ volatile ( + __asm__ volatile ( "movl $0xe0000, %%esi\n\t" "movl %0, %%edi\n\t" "movl $0x20000, %%ecx\n\t" "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop4) + "rep movsd\n\t" + ::"g"(memtop4) );*/ print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - @@ -537,22 +537,22 @@ g) Rx73h = 32h (unsigned char *) 0xe0000, 0x20000); /* restore the MTRR previously modified. */ -/* __asm__ volatile ( - "wbinvd\n\t" +/* __asm__ volatile ( + "wbinvd\n\t" "xorl %edx, %edx\n\t" "xorl %eax, %eax\n\t" "movl $0x204, %ecx\n\t" "wrmsr\n\t" - "movl $0x205, %ecx\n\t" - "wrmsr\n\t" + "movl $0x205, %ecx\n\t" + "wrmsr\n\t" "movl $0x206, %ecx\n\t" "wrmsr\n\t" - "movl $0x207, %ecx\n\t" - "wrmsr\n\t" - "movl $0x208, %ecx\n\t" - "wrmsr\n\t" - "movl $0x209, %ecx\n\t" - "wrmsr\n\t" + "movl $0x207, %ecx\n\t" + "wrmsr\n\t" + "movl $0x208, %ecx\n\t" + "wrmsr\n\t" + "movl $0x209, %ecx\n\t" + "wrmsr\n\t" );*/ } #endif diff --git a/src/northbridge/via/vx800/final_setting.c b/src/northbridge/via/vx800/final_setting.c index 97cc21820a..9ec31b58da 100644 --- a/src/northbridge/via/vx800/final_setting.c +++ b/src/northbridge/via/vx800/final_setting.c @@ -64,8 +64,8 @@ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMRegFinalValue() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 47a99c3cc1..03daeec342 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -230,7 +230,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) DramAttr->DramFreq = DIMMFREQ_200; DramAttr->DramCyc = 1000; } - //if set the frequence mannul + //if set the frequence mannul PRINT_DEBUG_MEM("Dram Frequency:"); PRINT_DEBUG_MEM_HEX16(DramAttr->DramFreq); PRINT_DEBUG_MEM(" \r"); diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 4dfe843bae..37e559c026 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -118,7 +118,7 @@ static u32 find_pci_tolm(struct bus *bus) static void pci_domain_set_resources(device_t dev) { - /* + /* * the order is important to find the correct ram size. */ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; diff --git a/src/northbridge/via/vx800/rank_map.c b/src/northbridge/via/vx800/rank_map.c index 6c88c68953..3eada63329 100644 --- a/src/northbridge/via/vx800/rank_map.c +++ b/src/northbridge/via/vx800/rank_map.c @@ -32,8 +32,8 @@ void DRAMPRToVRMapping(DRAM_SYS_ATTR * DramAttr); /*=================================================================== Function : DRAMBankInterleave() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : STEP 13 Set Bank Interleave VIANB3DRAMREG69[7:6] 00:No Interleave 01:2 Bank 10:4 Bank 11:8 Bank @@ -85,11 +85,11 @@ void DRAMBankInterleave(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSizingMATypeM() -Precondition : +Precondition : Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void - Purpose : STEP 14 1 DRAM Sizing 2 Fill MA type 3 Prank to vrankMapping + Purpose : STEP 14 1 DRAM Sizing 2 Fill MA type 3 Prank to vrankMapping ===================================================================*/ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr) { @@ -103,8 +103,8 @@ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMClearEndingAddress() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : clear Ending and Start adress from 0x40-4f to zero @@ -120,8 +120,8 @@ void DRAMClearEndingAddress(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSizingEachRank() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : Sizing each Rank invidually, by number of rows column banks pins, be care about 128bit @@ -189,8 +189,8 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSetRankMAType() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : set the matype Reg by MAMapTypeTbl, which the rule can be found in memoryinit @@ -258,11 +258,11 @@ void DRAMSetRankMAType(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSetEndingAddress() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void -Purpose : realize the Vrank 40...Reg (Start and Ending Regs). Vrank have same order with phy Rank, Size is actual Size +Purpose : realize the Vrank 40...Reg (Start and Ending Regs). Vrank have same order with phy Rank, Size is actual Size ===================================================================*/ void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr) { @@ -311,8 +311,8 @@ void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMPRToVRMapping() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : set the Vrank-prank map with the same order diff --git a/src/northbridge/via/vx800/timing_setting.c b/src/northbridge/via/vx800/timing_setting.c index a1d8e74812..7668b22e0b 100644 --- a/src/northbridge/via/vx800/timing_setting.c +++ b/src/northbridge/via/vx800/timing_setting.c @@ -72,7 +72,7 @@ void DRAMTimingSetting(DRAM_SYS_ATTR * DramAttr) /* Set DRAM Timing: CAS Latency for DDR1 -D0F3RX62 bit[0:2] for CAS Latency; +D0F3RX62 bit[0:2] for CAS Latency; */ void SetCL(DRAM_SYS_ATTR * DramAttr) { diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index 72420981ff..6fe8194922 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -139,7 +139,7 @@ void SetUMARam(void) // vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0); - //RxB2 may be for S.L. and RxB1 may be for L. L. + //RxB2 may be for S.L. and RxB1 may be for L. L. // It is different from Spec. ByteVal = SLD1F0Val; pci_write_config8(vga_dev, 0xb2, ByteVal); @@ -256,7 +256,7 @@ void SetUMARam(void) } outb(ByteVal, 0x03d5); - // Set frame buffer size + // Set frame buffer size outb(0x39, 0x03c4); outb(1 << SLD0F3Val, 0x03c5); @@ -295,7 +295,7 @@ void SetUMARam(void) SLBase = (RamSize << 26) - (UmaSize << 20); outb(0x6D, 0x03c4); - //SL Base[28:21] + //SL Base[28:21] outb((u8) ((SLBase >> 21) & 0xFF), 0x03c5); outb(0x6e, 0x03c4); diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 3897e010b5..7bdc3418f1 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -62,19 +62,19 @@ static int via_vx800_int15_handler(struct eregs *regs) case 0x5f18: { /* - * BL Bit[7:4] - * Memory Data Rate - * 0000: 66MHz - * 0001: 100MHz - * 0010: 133MHz - * 0011: 200MHz ( DDR200 ) - * 0100: 266MHz ( DDR266 ) - * 0101: 333MHz ( DDR333 ) - * 0110: 400MHz ( DDR400 ) - * 0111: 533MHz ( DDR I/II 533 + * BL Bit[7:4] + * Memory Data Rate + * 0000: 66MHz + * 0001: 100MHz + * 0010: 133MHz + * 0011: 200MHz ( DDR200 ) + * 0100: 266MHz ( DDR266 ) + * 0101: 333MHz ( DDR333 ) + * 0110: 400MHz ( DDR400 ) + * 0111: 533MHz ( DDR I/II 533 * 1000: 667MHz ( DDR I/II 667) - * Bit[3:0] - * N: Frame Buffer Size 2^N MB + * Bit[3:0] + * N: Frame Buffer Size 2^N MB */ u8 i; device_t dev; @@ -109,7 +109,7 @@ static int via_vx800_int15_handler(struct eregs *regs) case 0x5f02: regs->eax=0x5f; regs->ebx= (regs->ebx & 0xffff0000) | 2; - regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default res=0; break; @@ -118,7 +118,7 @@ static int via_vx800_int15_handler(struct eregs *regs) res = 0; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); regs->eax = 0; break; diff --git a/src/northbridge/via/vx800/vx800_early_serial.c b/src/northbridge/via/vx800/vx800_early_serial.c index 6462a2d295..8bac43ff12 100644 --- a/src/northbridge/via/vx800/vx800_early_serial.c +++ b/src/northbridge/via/vx800/vx800_early_serial.c @@ -70,7 +70,7 @@ static void enable_vx800_serial(void) // turn on pnp vx800_writepnpaddr(0x87); vx800_writepnpaddr(0x87); - // now go ahead and set up com1. + // now go ahead and set up com1. // set address vx800_writepnpaddr(0x7); vx800_writepnpdata(0x2); diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c index 7ba9b41acb..e40d54d721 100644 --- a/src/northbridge/via/vx800/vx800_early_smbus.c +++ b/src/northbridge/via/vx800/vx800_early_smbus.c @@ -171,10 +171,10 @@ static void enable_smbus(void) } /** - * A fixup for some systems that need time for the SMBus to "warm up". This is - * needed on some VT823x based systems, where the SMBus spurts out bad data for - * a short time after power on. This has been seen on the VIA Epia series and - * Jetway J7F2-series. It reads the ID byte from SMBus, looking for + * A fixup for some systems that need time for the SMBus to "warm up". This is + * needed on some VT823x based systems, where the SMBus spurts out bad data for + * a short time after power on. This has been seen on the VIA Epia series and + * Jetway J7F2-series. It reads the ID byte from SMBus, looking for * known-good data from a slot/address. Exits on either good data or a timeout. * * TODO: This should probably go into some global file, but one would need to diff --git a/src/northbridge/via/vx800/vx800_lpc.c b/src/northbridge/via/vx800/vx800_lpc.c index 874f32fbbd..ce2d822946 100644 --- a/src/northbridge/via/vx800/vx800_lpc.c +++ b/src/northbridge/via/vx800/vx800_lpc.c @@ -42,9 +42,9 @@ static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' }; //only I static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' }; //only INTA static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' }; //only INTA -static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' }; //all 4 +static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' }; //all 4 -static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' }; //only INTA +static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' }; //only INTA static unsigned char *pin_to_irq(const unsigned char *pin) { @@ -218,7 +218,7 @@ static void S3_ps2_kb_ms_wakeup(struct device *dev) pci_write_config8(dev, 0x51, enables); outb(inb(VX800_ACPI_IO_BASE + 0x02) | 0x20, VX800_ACPI_IO_BASE + 0x02); //ACPI golabe enable for sci smi trigger - outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22); //ACPI SCI on Internal KBC PME and mouse PME + outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22); //ACPI SCI on Internal KBC PME and mouse PME } @@ -354,17 +354,17 @@ static void southbridge_init(struct device *dev) fadt->pm2_cnt_len = 1;//to support cpu-c3 #2 ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) - #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. + #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. 1 enable SLP# asserts in C3 state PMIORx26<1> =1 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1 3 CLKRUN# is always asserted PMIORx26<3> =0 - 4 Disable PCISTP# When CLKRUN# is asserted - 1: PCISTP# will not assert When CLKRUN# is asserted + 4 Disable PCISTP# When CLKRUN# is asserted + 1: PCISTP# will not assert When CLKRUN# is asserted PMIORx26<4> =1 - 5 This bit controls whether the CPU voltage is lowered when in C3/S1 state. - VRDSLP will be active in either this bit set in C3 or LVL4 register read + 5 This bit controls whether the CPU voltage is lowered when in C3/S1 state. + VRDSLP will be active in either this bit set in C3 or LVL4 register read PMIORx26<0> =0 - 6 Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state PMIORx15 + 6 Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state PMIORx15 */ outb(0x17, VX800_ACPI_IO_BASE + 0x26); |