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-rw-r--r--src/northbridge/intel/haswell/chip.h1
-rw-r--r--src/northbridge/intel/haswell/gma.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h
index 28c082838d..73375d788d 100644
--- a/src/northbridge/intel/haswell/chip.h
+++ b/src/northbridge/intel/haswell/chip.h
@@ -17,7 +17,6 @@ struct northbridge_intel_haswell_config {
u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
- u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
u8 gpu_panel_power_cycle_delay; /* T4 time sequence */
u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
u16 gpu_panel_power_down_delay; /* T3 time sequence */
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index c466c09d86..5a6bb8e1de 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -304,7 +304,6 @@ static void gma_setup_panel(struct device *dev)
/* Setup Panel Power On Delays */
reg32 = gtt_read(PCH_PP_ON_DELAYS);
if (!reg32) {
- reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
gtt_write(PCH_PP_ON_DELAYS, reg32);