diff options
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/agesa/oem_s3.c | 12 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 13 | ||||
| -rw-r--r-- | src/northbridge/intel/common/mrc_cache.c | 7 |
3 files changed, 14 insertions, 18 deletions
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index fcf8ada4c5..c7d23ff346 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -97,15 +97,13 @@ static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) if (!flash) return -1; - flash->spi->rw = SPI_WRITE_FLAG; - spi_claim_bus(flash->spi); + spi_flash_volatile_group_begin(flash); - flash->erase(flash, pos, size); - flash->write(flash, pos, sizeof(len), &len); - flash->write(flash, pos + sizeof(len), len, buf); + spi_flash_erase(flash, pos, size); + spi_flash_write(flash, pos, sizeof(len), &len); + spi_flash_write(flash, pos + sizeof(len), len, buf); - flash->spi->rw = SPI_WRITE_FLAG; - spi_release_bus(flash->spi); + spi_flash_volatile_group_end(flash); return 0; #else return -1; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 97cadcb828..d3fc53b12f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -1140,20 +1140,17 @@ int8_t save_mct_information_to_nvram(void) return -1; } - /* Set up SPI flash access */ - flash->spi->rw = SPI_WRITE_FLAG; - spi_claim_bus(flash->spi); + spi_flash_volatile_group_begin(flash); /* Erase and write data structure */ - flash->erase(flash, s3nv_offset, CONFIG_S3_DATA_SIZE); - flash->write(flash, s3nv_offset, sizeof(struct amd_s3_persistent_data), persistent_data); + spi_flash_erase(flash, s3nv_offset, CONFIG_S3_DATA_SIZE); + spi_flash_write(flash, s3nv_offset, + sizeof(struct amd_s3_persistent_data), persistent_data); /* Deallocate temporary data structures */ free(persistent_data); - /* Tear down SPI flash access */ - flash->spi->rw = SPI_WRITE_FLAG; - spi_release_bus(flash->spi); + spi_flash_volatile_group_end(flash); /* Allow training bypass if DIMM configuration is unchanged on next boot */ nvram = 1; diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c index 4c3ee5d43c..a15812311b 100644 --- a/src/northbridge/intel/common/mrc_cache.c +++ b/src/northbridge/intel/common/mrc_cache.c @@ -212,7 +212,8 @@ static void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base); - flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); + spi_flash_erase(flash, to_flash_offset(flash, cache_base), + cache_size); /* we will start at the beginning again */ cache = cache_base; @@ -220,8 +221,8 @@ static void update_mrc_cache(void *unused) // 4. write mrc data with flash->write() printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", cache); - ret = flash->write(flash, to_flash_offset(flash, cache), - current->mrc_data_size + sizeof(*current), current); + ret = spi_flash_write(flash, to_flash_offset(flash, cache), + current->mrc_data_size + sizeof(*current), current); if (ret) printk(BIOS_WARNING, "Writing the MRC cache failed with ret %d\n", |