2 files changed, 30 insertions, 1 deletions
diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig
index b9c3547770..f7344ca97d 100644
--- a/src/northbridge/intel/i5000/Kconfig
+++ b/src/northbridge/intel/i5000/Kconfig
@@ -20,9 +20,17 @@
 config NORTHBRIDGE_INTEL_I5000
 	bool
 	select MMCONF_SUPPORT
+	select MMCONF_SUPPORT_DEFAULT
 	select HAVE_DEBUG_RAM_SETUP
 
+if NORTHBRIDGE_INTEL_I5000
+
 config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
 	bool
 	prompt "Run ramcheck after RAM initialization"
-	depends on NORTHBRIDGE_INTEL_I5000
+
+config BOOTBLOCK_NORTHBRIDGE_INIT
+	string
+	default "northbridge/intel/i5000/bootblock.c"
+
+endif
diff --git a/src/northbridge/intel/i5000/bootblock.c b/src/northbridge/intel/i5000/bootblock.c
new file mode 100644
index 0000000000..eabbee6d63
--- /dev/null
+++ b/src/northbridge/intel/i5000/bootblock.c
@@ -0,0 +1,21 @@
+#include <arch/io.h>
+
+static void bootblock_northbridge_init(void)
+{
+	/*
+	 * The "io" variant of the config access is explicitly used to
+	 * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+	 * to true. That way all subsequent non-explicit config accesses use
+	 * MCFG. This code also assumes that bootblock_northbridge_init() is
+	 * the first thing called in the non-asm boot block code. The final
+	 * assumption is that no assembly code is using the
+	 * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+	 *
+	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
+	 * 4GiB.
+	 */
+
+	/* setup PCIe MMCONF base address */
+	pci_io_write_config32(PCI_DEV(0, 16, 0), 0x64,
+			   CONFIG_MMCONF_BASE_ADDRESS >> 16);
+}