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-rw-r--r--src/northbridge/via/cn700/Makefile.inc1
-rw-r--r--src/northbridge/via/cn700/raminit.c6
-rw-r--r--src/northbridge/via/cn700/raminit.h5
3 files changed, 11 insertions, 1 deletions
diff --git a/src/northbridge/via/cn700/Makefile.inc b/src/northbridge/via/cn700/Makefile.inc
index b6e7875099..f7f288f732 100644
--- a/src/northbridge/via/cn700/Makefile.inc
+++ b/src/northbridge/via/cn700/Makefile.inc
@@ -19,5 +19,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_VIA_CN700),y)
ramstage-y += northbridge.c
ramstage-y += agp.c
ramstage-y += vga.c
+romstage-y += raminit.c
endif
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 9cfd952f1e..8689ec97e3 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -16,6 +16,10 @@
* GNU General Public License for more details.
*/
+#include <stdint.h>
+#include <arch/io.h>
+#include <northbridge/via/cn700/raminit.h>
+#include <console/console.h>
#include <spd.h>
#include <delay.h>
#include "cn700.h"
@@ -446,7 +450,7 @@ static void sdram_enable(pci_devfn_t dev, u8 *rank_address)
/*
* Support one DIMM with up to 2 ranks.
*/
-static void ddr_ram_setup(const struct mem_controller *ctrl)
+void ddr_ram_setup(const struct mem_controller *ctrl)
{
u8 reg;
diff --git a/src/northbridge/via/cn700/raminit.h b/src/northbridge/via/cn700/raminit.h
index 80e085fc6f..073b2531ba 100644
--- a/src/northbridge/via/cn700/raminit.h
+++ b/src/northbridge/via/cn700/raminit.h
@@ -24,4 +24,9 @@ struct mem_controller {
u8 channel0[DIMM_SOCKETS];
};
+void ddr_ram_setup(const struct mem_controller *ctrl);
+
+/* mainboard specific */
+int spd_read_byte(unsigned device, unsigned address);
+
#endif