4 files changed, 35 insertions, 9 deletions
diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc
index 355d9b2524..57025859d3 100644
--- a/src/northbridge/intel/i440bx/Makefile.inc
+++ b/src/northbridge/intel/i440bx/Makefile.inc
@@ -19,6 +19,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y)
 ramstage-y += northbridge.c
 
 romstage-y += raminit.c
+romstage-y += romstage.c
 romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c
 romstage-y += memmap.c
 
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 08019880b7..597ba946b4 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -667,7 +667,7 @@ static void spd_enable_refresh(void)
 Public interface.
 -----------------------------------------------------------------------------*/
 
-void sdram_set_registers(void)
+static void sdram_set_registers(void)
 {
 	int i, max;
 	uint8_t reg;
@@ -977,7 +977,7 @@ static void set_dram_row_attributes(void)
 	PRINT_DEBUG("DRAMC has been set to 0x%02x\n", value);
 }
 
-void sdram_set_spd_registers(void)
+static void sdram_set_spd_registers(void)
 {
 	/* Setup DRAM row boundary registers and other attributes. */
 	set_dram_row_attributes();
@@ -993,7 +993,7 @@ void sdram_set_spd_registers(void)
 	pci_write_config8(NB, DRAMT, 0x03);
 }
 
-void sdram_enable(void)
+static void sdram_enable(void)
 {
 	int i;
 
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index 347c1fecd7..1e9f25b8be 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -22,13 +22,8 @@
 
 void enable_spd(void);
 void disable_spd(void);
-
-/* Function prototypes. */
-void sdram_set_registers(void);
-void sdram_set_spd_registers(void);
-void sdram_enable(void);
-/* A merger of above functions */
 void sdram_initialize(void);
+void mainboard_enable_serial(void);
 
 /* Debug */
 #if CONFIG(DEBUG_RAM_SETUP)
diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c
new file mode 100644
index 0000000000..1dee03a984
--- /dev/null
+++ b/src/northbridge/intel/i440bx/romstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/romstage.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <southbridge/intel/i82371eb/i82371eb.h>
+#include <northbridge/intel/i440bx/raminit.h>
+
+void mainboard_romstage_entry(void)
+{
+	mainboard_enable_serial();
+	console_init();
+
+	i82371eb_early_init();
+
+	sdram_initialize();
+	cbmem_initialize_empty();
+}