diff options
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.h | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.c | 2 |
3 files changed, 0 insertions, 15 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 60a218b419..3fd8cb0b3d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -4078,18 +4078,6 @@ void normalize_training(ramctr_timing *ctrl) } } -void write_controller_mr(ramctr_timing *ctrl) -{ - int channel, slotrank; - - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) = - make_mr0(ctrl, slotrank); - MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) = - make_mr1(ctrl, slotrank, channel); - } -} - int channel_test(ramctr_timing *ctrl) { int channel, slotrank, lane; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 5b08ce5ba6..a6f4e0ba85 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -244,7 +244,6 @@ int discover_edges(ramctr_timing *ctrl); int discover_edges_write(ramctr_timing *ctrl); int discover_timC_write(ramctr_timing *ctrl); void normalize_training(ramctr_timing *ctrl); -void write_controller_mr(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl); void set_scrambling_seed(ramctr_timing *ctrl); void set_wmm_behavior(const u32 cpu); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 844e69af3b..53017eb8c2 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -715,8 +715,6 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ set_read_write_timings(ctrl); - write_controller_mr(ctrl); - if (!s3resume) { err = channel_test(ctrl); if (err) |