diff options
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/gx2/northbridge.c | 29 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/pll_reset.c | 11 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/raminit.c | 13 |
3 files changed, 25 insertions, 28 deletions
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 85961f48b7..fb3cb1c1e0 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -155,11 +155,16 @@ setup_gx2_cache(void) wbinvd(); return sizembytes; } + +#define SMM_OFFSET 0x40400000 +#define SMM_SIZE 256 + /* we have to do this here. We have not found a nicer way to do it */ void setup_gx2(void) { int i; + unsigned long tmp, tmp2, tmp3; msr_t msr; unsigned long sizem, membytes; @@ -169,10 +174,10 @@ setup_gx2(void) /* we need to set 0x10000028 and 0x40000029 */ printk_debug("sizem 0x%x, membytes 0x%x\n", sizem, membytes); - msr.hi = 0x20000000 | membytes >>24; + msr.hi = 0x20000000 | membytes>>24; msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20); wrmsr(0x10000028, msr); - msr.hi = 0x20000000 | membytes >>24; + msr.hi = 0x20000000 | membytes>>24; msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20); wrmsr(0x40000029, msr); msr = rdmsr(0x10000028); @@ -181,6 +186,22 @@ setup_gx2(void) printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo); + /* fixme: SMM MSR 0x10000026 and 0x400000023 */ + /* calculate the OFFSET field */ + tmp = membytes - SMM_OFFSET; + tmp >>= 12; + tmp <<= 8; + tmp |= 0x20000000; + tmp |= (SMM_OFFSET >> 24); + + /* calculate the PBASE and PMASK fields */ + tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */ + tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff); + printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2); + msr.hi = tmp; + msr.lo = tmp2; + wrmsr(0x10000026, msr); + /* now do the default MSR values */ for(i = 0; msr_defaults[i].msr_no; i++) { msr_t msr; @@ -383,11 +404,11 @@ static void enable_dev(struct device *dev) cpubug(); setup_gx2(); /* do this here for now -- this chip really breaks our device model */ + setup_realmode_idt(); do_vsmbios(); dev->ops = &pci_domain_ops; pci_set_method(dev); - } - else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { printk_debug("DEVICE_PATH_APIC_CLUSTER\n"); dev->ops = &cpu_bus_ops; diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index e1696fd703..ea54c49277 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -86,17 +86,6 @@ static const unsigned char fbdiv2plldiv[] = { 49, 40, 19, 59, 32, 54, 35, 0, 41, 60, 55, 0, 61, 0, 0, 0 }; -static const unsigned char pci33_sdr_crt [] = { - /* FbDIV, VDIV, MDIV CPU/GeodeLink */ - 12, 2, 4, // 200/100 - 16, 2, 4, // 266/133 - 18, 2, 5, // 300/120 - 20, 2, 5, // 333/133 - 22, 2, 6, // 366/122 - 24, 2, 6, // 400/133 - 26, 2, 6 // 433/144 -}; - static const unsigned char pci33_ddr_crt [] = { /* FbDIV, VDIV, MDIV CPU/GeodeLink */ 12, 2, 3, // 200/133 diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index f0156c3183..636c60b9d2 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -4,19 +4,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl) { } -#if 0 -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - msr_t mst; - unsigned char val; - - /* get module banks per dimm, SPD byte 5 */ - val = spd_read_byte(0xA0, 5); - if (val < 1 || val > 2) - print_err("Module banks per dimm"); - -} -#endif /* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */ static void sdram_enable(int controllers, const struct mem_controller *ctrl) |