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-rw-r--r--src/northbridge/intel/i945/bootblock.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index f4b46282ca..edb9a8d4d0 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
+#include <arch/pci_io_cfg.h>
#include <assert.h>
-#include <device/pci_ops.h>
#include <types.h>
+
#include "i945.h"
static uint32_t encode_pciexbar_length(void)
@@ -27,6 +28,6 @@ void bootblock_early_northbridge_init(void)
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
- const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
- pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
+ const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}