diff options
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/chip.h | 10 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 12 |
2 files changed, 11 insertions, 11 deletions
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 73375d788d..b1c8d37a74 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -17,11 +17,11 @@ struct northbridge_intel_haswell_config { u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ - u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ - u16 gpu_panel_power_down_delay; /* T3 time sequence */ - u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ - u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + u16 gpu_panel_power_cycle_delay_ms; /* T4 time sequence */ + u16 gpu_panel_power_up_delay_ms; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay_ms; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay_ms; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay_ms; /* Tx time sequence */ unsigned int gpu_pch_backlight_pwm_hz; enum { diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 71d5ab61ec..7adcfdaa5c 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -257,24 +257,24 @@ static void gma_setup_panel(struct device *dev) /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + reg32 |= ((conf->gpu_panel_power_up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_ON_DELAYS, reg32); } /* Setup Panel Power Off Delays */ reg32 = gtt_read(PCH_PP_OFF_DELAYS); if (!reg32) { - reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + reg32 = ((conf->gpu_panel_power_down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_OFF_DELAYS, reg32); } /* Setup Panel Power Cycle Delay */ - if (conf->gpu_panel_power_cycle_delay) { + if (conf->gpu_panel_power_cycle_delay_ms) { reg32 = gtt_read(PCH_PP_DIVISOR); reg32 &= ~0x1f; - reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; + reg32 |= (DIV_ROUND_UP(conf->gpu_panel_power_cycle_delay_ms, 100) + 1) & 0x1f; gtt_write(PCH_PP_DIVISOR, reg32); } |