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-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c35
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.h1
-rw-r--r--src/northbridge/intel/sandybridge/raminit_native.c35
3 files changed, 35 insertions, 36 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 3ab8df2403..60a218b419 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -80,41 +80,6 @@ static u32 get_XOVER_CMD(u8 rankmap)
return reg;
}
-/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */
-u8 get_CWL(u32 tCK)
-{
- /* Get CWL based on tCK using the following rule */
- switch (tCK) {
- case TCK_1333MHZ:
- return 12;
-
- case TCK_1200MHZ:
- case TCK_1100MHZ:
- return 11;
-
- case TCK_1066MHZ:
- case TCK_1000MHZ:
- return 10;
-
- case TCK_933MHZ:
- case TCK_900MHZ:
- return 9;
-
- case TCK_800MHZ:
- case TCK_700MHZ:
- return 8;
-
- case TCK_666MHZ:
- return 7;
-
- case TCK_533MHZ:
- return 6;
-
- default:
- return 5;
- }
-}
-
void dram_find_common_params(ramctr_timing *ctrl)
{
size_t valid_dimms;
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 32f2b44d4b..5b08ce5ba6 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -227,7 +227,6 @@ typedef struct ramctr_timing_st {
#define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1)
#define GET_ERR_CHANNEL(x) (x >> 16)
-u8 get_CWL(u32 tCK);
void dram_mrscommands(ramctr_timing *ctrl);
void program_timings(ramctr_timing *ctrl, int channel);
void dram_find_common_params(ramctr_timing *ctrl);
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 326197b9bd..844e69af3b 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -42,6 +42,41 @@ static u32 get_FRQ(const ramctr_timing *ctrl)
die("Unsupported CPU or base frequency.");
}
+/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */
+static u8 get_CWL(u32 tCK)
+{
+ /* Get CWL based on tCK using the following rule */
+ switch (tCK) {
+ case TCK_1333MHZ:
+ return 12;
+
+ case TCK_1200MHZ:
+ case TCK_1100MHZ:
+ return 11;
+
+ case TCK_1066MHZ:
+ case TCK_1000MHZ:
+ return 10;
+
+ case TCK_933MHZ:
+ case TCK_900MHZ:
+ return 9;
+
+ case TCK_800MHZ:
+ case TCK_700MHZ:
+ return 8;
+
+ case TCK_666MHZ:
+ return 7;
+
+ case TCK_533MHZ:
+ return 6;
+
+ default:
+ return 5;
+ }
+}
+
/* Get REFI based on frequency index, tREFI = 7.8usec */
static u32 get_REFI(u32 FRQ, u8 base_freq)
{