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-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c102
-rw-r--r--src/northbridge/amd/amdht/ht_wrapper.c107
-rw-r--r--src/northbridge/amd/amdht/ht_wrapper.h25
3 files changed, 213 insertions, 21 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 6d91cbd00d..74cecc894a 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -187,6 +187,43 @@ static void ht_route_link(struct bus *link, scan_state mode)
}
}
+static void amd_g34_fixup(struct bus *link, device_t dev)
+{
+ uint32_t nodeid = amdfam10_nodeid(dev);
+ uint8_t rev_gte_d = 0;
+ uint8_t dual_node = 0;
+ uint32_t f3xe8;
+
+ if (cpuid_eax(0x80000001) >= 0x8)
+ /* Revision D or later */
+ rev_gte_d = 1;
+
+ if (rev_gte_d) {
+ f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
+
+ /* Check for dual node capability */
+ if (f3xe8 & 0x20000000)
+ dual_node = 1;
+
+ if (dual_node) {
+ /* Each G34 processor contains a defective HT link.
+ * See the BKDG Rev 3.62 section 2.7.1.5 for details.
+ */
+ f3xe8 = pci_read_config32(get_node_pci(nodeid, 3), 0xe8);
+ uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30);
+ if (internal_node_number == 0) {
+ /* Node 0 */
+ if (link->link_num == 6) /* Link 2 Sublink 1 */
+ printk(BIOS_DEBUG, "amdfam10_scan_chain(): node %d (internal node ID %d): skipping defective HT link\n", nodeid, internal_node_number);
+ } else {
+ /* Node 1 */
+ if (link->link_num == 5) /* Link 1 Sublink 1 */
+ printk(BIOS_DEBUG, "amdfam10_scan_chain(): node %d (internal node ID %d): skipping defective HT link\n", nodeid, internal_node_number);
+ }
+ }
+ }
+}
+
static void amdfam10_scan_chain(struct bus *link)
{
unsigned int next_unitid;
@@ -277,8 +314,11 @@ static void amdfam10_scan_chains(device_t dev)
trim_ht_chain(dev);
for (link = dev->link_list; link; link = link->next) {
- if (link->ht_link_up)
+ if (link->ht_link_up) {
+ if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
+ amd_g34_fixup(link, dev);
amdfam10_scan_chain(link);
+ }
}
}
@@ -323,8 +363,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi
if (result == 1) {
/* I have been allocated this one */
break;
- }
- else if (result > 1) {
+ } else if (result > 1) {
/* I have a free register pair */
free_reg = reg;
}
@@ -357,8 +396,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link
if (result == 1) {
/* I have been allocated this one */
break;
- }
- else if (result > 1) {
+ } else if (result > 1) {
/* I have a free register pair */
free_reg = reg;
}
@@ -473,8 +511,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource,
set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8);
- }
- else if (resource->flags & IORESOURCE_MEM) {
+ } else if (resource->flags & IORESOURCE_MEM) {
set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8]
store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8);
}
@@ -799,8 +836,7 @@ static void amdfam10_domain_set_resources(device_t dev)
}
if ((basek + sizek) <= 4*1024*1024) {
sizek = 0;
- }
- else {
+ } else {
basek = 4*1024*1024;
sizek -= (4*1024*1024 - mmio_basek);
}
@@ -977,8 +1013,7 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
if (dimm_size_bytes > 0x800000000) {
t->size = 0x7FFF;
t->extended_size = dimm_size_bytes;
- }
- else {
+ } else {
t->size = dimm_size_bytes / (1024*1024);
t->size &= (~0x8000); /* size specified in megabytes */
}
@@ -1005,8 +1040,7 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
t->part_number = smbios_add_string(t->eos, mem_info->dct_stat[node].DimmPartNumber[slot]);
if (mem_info->dct_stat[node].DimmSerialNumber[slot] == 0) {
t->serial_number = smbios_add_string(t->eos, "None");
- }
- else {
+ } else {
snprintf(string_buffer, sizeof (string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]);
t->serial_number = smbios_add_string(t->eos, string_buffer);
}
@@ -1108,8 +1142,7 @@ static void add_more_links(device_t dev, unsigned total_links)
memset(link, 0, links*sizeof(*link));
last->next = link;
}
- }
- else {
+ } else {
link = malloc(total_links*sizeof(*link));
memset(link, 0, total_links*sizeof(*link));
dev->link_list = link;
@@ -1244,6 +1277,10 @@ static void cpu_bus_scan(device_t dev)
unsigned busn, devn;
struct bus *pbus;
+ uint8_t rev_gte_d = 0;
+ uint8_t dual_node = 0;
+ uint32_t f3xe8;
+
busn = CONFIG_CBB;
devn = CONFIG_CDB+i;
pbus = dev_mc->bus;
@@ -1268,6 +1305,7 @@ static void cpu_bus_scan(device_t dev)
}
}
+
/* Ok, We need to set the links for that device.
* otherwise the device under it will not be scanned
*/
@@ -1279,6 +1317,17 @@ static void cpu_bus_scan(device_t dev)
if (cdb_dev)
add_more_links(cdb_dev, 4);
+ f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
+
+ if (cpuid_eax(0x80000001) >= 0x8)
+ /* Revision D or later */
+ rev_gte_d = 1;
+
+ if (rev_gte_d)
+ /* Check for dual node capability */
+ if (f3xe8 & 0x20000000)
+ dual_node = 1;
+
cores_found = 0; // one core
cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
int enable_node = cdb_dev && cdb_dev->enabled;
@@ -1290,6 +1339,9 @@ static void cpu_bus_scan(device_t dev)
printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cdb_dev), cores_found);
}
+ if (siblings > cores_found)
+ siblings = cores_found;
+
u32 jj;
if(disable_siblings) {
jj = 0;
@@ -1299,7 +1351,20 @@ static void cpu_bus_scan(device_t dev)
}
for (j = 0; j <=jj; j++ ) {
- u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ?
+ u32 apic_id;
+
+ if (dual_node) {
+ apic_id = 0;
+ if (nb_cfg_54) {
+ apic_id |= ((i >> 1) & 0x3) << 4; /* Node ID */
+ apic_id |= ((i & 0x1) * (siblings + 1)) + j; /* Core ID */
+ } else {
+ apic_id |= i & 0x3; /* Node ID */
+ apic_id |= (((i & 0x1) * (siblings + 1)) + j) << 4; /* Core ID */
+ }
+ } else {
+ apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ?
+ }
#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0)
if(sysconf.enabled_apic_ext_id) {
@@ -1311,7 +1376,7 @@ static void cpu_bus_scan(device_t dev)
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
if (cpu)
amd_cpu_topology(cpu, i, j);
- } //j
+ }
}
}
@@ -1356,8 +1421,7 @@ static void root_complex_enable_dev(struct device *dev)
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index 36fe60bf7a..389b1b1568 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -22,6 +22,8 @@
#include <console/console.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
+#include "ht_wrapper.h"
+
/*----------------------------------------------------------------------------
* TYPEDEFS, DEFINITIONS AND MACROS
*
@@ -113,6 +115,20 @@ void getAmdTopolist(u8 ***p)
*p = (u8 **)amd_topo_list;
}
+/**
+ * BOOL AMD_CB_IgnoreLink(u8 Node, u8 Link)
+ * Description:
+ * This routine is used to ignore connected yet faulty HT links,
+ * such as those present in a G34 processor package.
+ *
+ * Parameters:
+ * @param[in] node = The node on which this chain is located
+ * @param[in] link = The link on the host for this chain
+ */
+static BOOL AMD_CB_IgnoreLink (u8 node, u8 link)
+{
+ return 0;
+}
/**
* void amd_ht_init(struct sys_info *sysinfo)
@@ -128,7 +144,7 @@ static void amd_ht_init(struct sys_info *sysinfo)
0, // u8 AutoBusStart;
32, // u8 AutoBusMax;
6, // u8 AutoBusIncrement;
- NULL, // BOOL (*AMD_CB_IgnoreLink)();
+ AMD_CB_IgnoreLink, // BOOL (*AMD_CB_IgnoreLink)();
NULL, // BOOL (*AMD_CB_OverrideBusNumbers)();
AMD_CB_ManualBUIDSwapList, // BOOL (*AMD_CB_ManualBUIDSwapList)();
NULL, // void (*AMD_CB_DeviceCapOverride)();
@@ -146,6 +162,93 @@ static void amd_ht_init(struct sys_info *sysinfo)
printk(BIOS_DEBUG, "Enter amd_ht_init()\n");
amdHtInitialize(&ht_wrapper);
printk(BIOS_DEBUG, "Exit amd_ht_init()\n");
+}
-
+/**
+ * void amd_ht_fixup(struct sys_info *sysinfo)
+ *
+ * AMD HT fixup
+ *
+ */
+void amd_ht_fixup(struct sys_info *sysinfo) {
+ printk(BIOS_DEBUG, "amd_ht_fixup()\n");
+ if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) {
+ uint8_t rev_gte_d = 0;
+ uint8_t dual_node = 0;
+ uint32_t f3xe8;
+ uint32_t family;
+ uint32_t model;
+
+ family = model = cpuid_eax(0x80000001);
+ model = ((model & 0xf0000) >> 16) | ((model & 0xf0) >> 4);
+
+ if (model >= 0x8)
+ /* Revision D or later */
+ rev_gte_d = 1;
+
+ if (rev_gte_d) {
+ f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
+
+ /* Check for dual node capability */
+ if (f3xe8 & 0x20000000)
+ dual_node = 1;
+
+ if (dual_node) {
+ /* Each G34 processor contains a defective HT link.
+ * See the BKDG Rev 3.62 section 2.7.1.5 for details.
+ */
+ uint8_t node;
+ uint8_t node_count = get_nodes();
+ uint32_t dword;
+ for (node = 0; node < node_count; node++) {
+ f3xe8 = pci_read_config32(NODE_PCI(node, 3), 0xe8);
+ uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30);
+ printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link\n", node, internal_node_number);
+ if (internal_node_number == 0) {
+ uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), 0xd8) & 0x1;
+ if (package_link_3_connected) {
+ /* Set WidthIn and WidthOut to 0 */
+ dword = pci_read_config32(NODE_PCI(node, 0), 0xc4);
+ dword &= ~0x77000000;
+ pci_write_config32(NODE_PCI(node, 0), 0xc4, dword);
+ /* Set Ganged to 1 */
+ dword = pci_read_config32(NODE_PCI(node, 0), 0x178);
+ dword |= 0x00000001;
+ pci_write_config32(NODE_PCI(node, 0), 0x178, dword);
+ } else {
+ /* Set ConnDly to 1 */
+ dword = pci_read_config32(NODE_PCI(node, 0), 0x16c);
+ dword |= 0x00000100;
+ pci_write_config32(NODE_PCI(node, 0), 0x16c, dword);
+ /* Set TransOff and EndOfChain to 1 */
+ dword = pci_read_config32(NODE_PCI(node, 4), 0xc4);
+ dword |= 0x000000c0;
+ pci_write_config32(NODE_PCI(node, 4), 0xc4, dword);
+ }
+ } else if (internal_node_number == 1) {
+ uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), 0xb8) & 0x1;
+ if (package_link_3_connected) {
+ /* Set WidthIn and WidthOut to 0 */
+ dword = pci_read_config32(NODE_PCI(node, 0), 0xa4);
+ dword &= ~0x77000000;
+ pci_write_config32(NODE_PCI(node, 0), 0xa4, dword);
+ /* Set Ganged to 1 */
+ dword = pci_read_config32(NODE_PCI(node, 0), 0x174);
+ dword |= 0x00000001;
+ pci_write_config32(NODE_PCI(node, 0), 0x174, dword);
+ } else {
+ /* Set ConnDly to 1 */
+ dword = pci_read_config32(NODE_PCI(node, 0), 0x16c);
+ dword |= 0x00000100;
+ pci_write_config32(NODE_PCI(node, 0), 0x16c, dword);
+ /* Set TransOff and EndOfChain to 1 */
+ dword = pci_read_config32(NODE_PCI(node, 4), 0xa4);
+ dword |= 0x000000c0;
+ pci_write_config32(NODE_PCI(node, 4), 0xa4, dword);
+ }
+ }
+ }
+ }
+ }
+ }
}
diff --git a/src/northbridge/amd/amdht/ht_wrapper.h b/src/northbridge/amd/amdht/ht_wrapper.h
new file mode 100644
index 0000000000..3e9d957a8d
--- /dev/null
+++ b/src/northbridge/amd/amdht/ht_wrapper.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef AMD_HT_WRAPPER_H
+#define AMD_HT_WRAPPER_H
+
+void amd_ht_fixup(struct sys_info *sysinfo);
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 07:46:09 +0000