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-rw-r--r--src/northbridge/amd/amdk8/early_ht.c8
-rw-r--r--src/northbridge/amd/amdk8/misc_control.c15
-rw-r--r--src/northbridge/amd/amdk8/raminit.c104
3 files changed, 41 insertions, 86 deletions
diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index be79545531..af9453492b 100644
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -16,8 +16,9 @@ static int enumerate_ht_chain(void)
id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
/* If the chain is enumerated quit */
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000))
+ {
break;
}
hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
@@ -25,7 +26,8 @@ static int enumerate_ht_chain(void)
hdr_type &= 0x7f;
if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
- (hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
+ (hdr_type == PCI_HEADER_TYPE_BRIDGE))
+ {
pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
}
while(pos != 0) {
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 4938c453d7..e5e8f4c78f 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -42,7 +42,7 @@ static void mcf3_read_resources(device_t dev)
pci_dev_read_resources(dev);
/* If we are not the first processor don't allocate the gart apeture */
- if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 0x3)) {
+ if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 3)) {
return;
}
@@ -68,19 +68,20 @@ static void set_agp_aperture(device_t dev)
if (resource) {
device_t pdev;
uint32_t gart_base, gart_acr;
+
/* Remember this resource has been stored */
resource->flags |= IORESOURCE_STORED;
- /*Find the size of the GART aperture */
- gart_acr = (0<<6)|(0<<5)|(0<<4)| ((log2(resource->size) - 25) << 1)|(0<<0);
+ /* Find the size of the GART aperture */
+ gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
/* Get the base address */
gart_base = ((resource->base) >> 25) & 0x00007fff;
/* Update the other northbriges */
pdev = 0;
- while (pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev)) {
- /* Store GART size but don't enable it */
+ while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
+ /* Store the GART size but don't enable it */
pci_write_config32(pdev, 0x90, gart_acr);
/* Store the GART base address */
@@ -175,8 +176,6 @@ static void misc_control_init(struct device *dev)
needs_reset = 1; /* Needed? */
}
}
-#if CONFIG_MAX_CPUS > 1
-/* Single CPU systems don't seem to need this. It might cause resets? (YhLu) */
/* Optimize the Link read pointers */
f0_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3);
if (f0_dev) {
@@ -202,7 +201,6 @@ static void misc_control_init(struct device *dev)
else {
printk_err("Missing f0 device!\n");
}
-#endif
if (needs_reset) {
printk_debug("resetting cpu\n");
hard_reset();
@@ -217,6 +215,7 @@ static struct device_operations mcf3_ops = {
.enable_resources = pci_dev_enable_resources,
.init = misc_control_init,
.scan_bus = 0,
+ .ops_pci = 0,
};
static struct pci_driver mcf3_driver __pci_driver = {
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 67ae757a32..e4043493ab 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -1,20 +1,20 @@
-#include <cpu/k8/mtrr.h>
+#include <cpu/x86/mem.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
#include "raminit.h"
#include "amdk8.h"
#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
# error "CONFIG_LB_MEM_TOPK must be a power of 2"
#endif
-
static void setup_resource_map(const unsigned int *register_values, int max)
{
int i;
print_debug("setting up resource map....");
-
#if 0
print_debug("\r\n");
#endif
- for (i = 0; i < max; i += 3) {
+ for(i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
unsigned long reg;
@@ -1921,11 +1921,21 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct
return dimm_mask;
}
+static int controller_present(const struct mem_controller *ctrl)
+{
+ return pci_read_config32(ctrl->f0, 0) == 0x11001022;
+}
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
struct spd_set_memclk_result result;
const struct mem_param *param;
long dimm_mask;
+#if 1
+ if (!controller_present(ctrl)) {
+ print_debug("No memory controller present\r\n");
+ return;
+ }
+#endif
hw_enable_ecc(ctrl);
activate_spd_rom(ctrl);
dimm_mask = spd_detect_dimms(ctrl);
@@ -1972,6 +1982,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Before enabling memory start the memory clocks */
for(i = 0; i < controllers; i++) {
uint32_t dch;
+ if (!controller_present(ctrl + i))
+ continue;
dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
if (dch & (DCH_MEMCLK_EN0|DCH_MEMCLK_EN1|DCH_MEMCLK_EN2|DCH_MEMCLK_EN3)) {
dch |= DCH_MEMCLK_VALID;
@@ -1991,6 +2003,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for(i = 0; i < controllers; i++) {
uint32_t dcl, dch;
+ if (!controller_present(ctrl + i))
+ continue;
/* Skip everything if I don't have any memory on this controller */
dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
if (!(dch & DCH_MEMCLK_VALID)) {
@@ -2021,6 +2035,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
}
for(i = 0; i < controllers; i++) {
uint32_t dcl, dch;
+ if (!controller_present(ctrl + i))
+ continue;
/* Skip everything if I don't have any memory on this controller */
dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
if (!(dch & DCH_MEMCLK_VALID)) {
@@ -2058,78 +2074,16 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Save the value of msr_201 */
msr_201 = rdmsr(0x201);
- print_debug("Clearing LinuxBIOS memory: ");
-
- /* disable cache */
- __asm__ volatile(
- "movl %%cr0, %0\n\t"
- "orl $0x40000000, %0\n\t"
- "movl %0, %%cr0\n\t"
- :"=r" (cnt)
- );
-
- /* Disable fixed mtrrs */
- msr = rdmsr(MTRRdefType_MSR);
- msr.lo &= ~(1<<10);
- wrmsr(MTRRdefType_MSR, msr);
-
-
- /* Set the variable mtrrs to write combine */
- msr.hi = 0;
- msr.lo = 0 | MTRR_TYPE_WRCOMB;
- wrmsr(0x200, msr);
-
- /* Set the limit to 1M of ram */
- msr.hi = 0x000000ff;
- msr.lo = (~((CONFIG_LB_MEM_TOPK << 10) - 1)) | 0x800;
- wrmsr(0x201, msr);
-
- /* enable cache */
- __asm__ volatile(
- "movl %%cr0, %0\n\t"
- "andl $0x9fffffff, %0\n\t"
- "movl %0, %%cr0\n\t"
- :"=r" (cnt)
- );
-
+ print_debug("Clearing initial memory region: ");
+
+ /* Use write combine caching while we setup the first 1M */
+ cache_lbmem(MTRR_TYPE_WRCOMB);
+
/* clear memory 1meg */
- __asm__ volatile(
- "1: \n\t"
- "movl %0, %%fs:(%1)\n\t"
- "addl $4,%1\n\t"
- "subl $4,%2\n\t"
- "jnz 1b\n\t"
- :
- : "a" (0), "D" (0), "c" (1024*1024)
- );
-
- /* disable cache */
- __asm__ volatile(
- "movl %%cr0, %0\n\t"
- "orl $0x40000000, %0\n\t"
- "movl %0, %%cr0\n\t"
- :"=r" (cnt)
- );
-
- /* restore msr registers */
- msr = rdmsr(MTRRdefType_MSR);
- msr.lo |= 0x0400;
- wrmsr(MTRRdefType_MSR, msr);
-
-
- /* Restore the variable mtrrs */
- msr.hi = 0;
- msr.lo = MTRR_TYPE_WRBACK;
- wrmsr(0x200, msr);
- wrmsr(0x201, msr_201);
-
- /* enable cache */
- __asm__ volatile(
- "movl %%cr0, %0\n\t"
- "andl $0x9fffffff, %0\n\t"
- "movl %0, %%cr0\n\t"
- :"=r" (cnt)
- );
+ clear_memory((void *)0, CONFIG_LB_MEM_TOPK << 10);
+
+ /* The first 1M is now setup, use it */
+ cache_lbmem(MTRR_TYPE_WRBACK);
print_debug(" done\r\n");
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 11:24:46 +0000