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-rw-r--r--src/northbridge/intel/gm45/raminit.c3
-rw-r--r--src/northbridge/intel/x4x/romstage.c2
2 files changed, 0 insertions, 5 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index b1da177281..5b8d1d811e 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1723,9 +1723,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
while (!(read8((u8 *)0xfed40000) & (1 << 7))) {}
}
- /* Enable SMBUS. */
- enable_smbus();
-
/* Collect information about DIMMs and find common settings. */
collect_dimm_config(sysinfo);
diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c
index eae87f3674..26d336bfd2 100644
--- a/src/northbridge/intel/x4x/romstage.c
+++ b/src/northbridge/intel/x4x/romstage.c
@@ -34,8 +34,6 @@ void mainboard_romstage_entry(void)
u8 boot_path = 0;
u8 s3_resume;
- enable_smbus();
-
#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
i82801jx_early_init();
#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)