diff options
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/gm45/romstage.c | 7 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/romstage.c | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 9 |
3 files changed, 6 insertions, 19 deletions
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 38f2d5f68f..7c16761bb5 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <arch/acpi.h> #include <cpu/x86/lapic.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/gm45/gm45.h> #include <southbridge/intel/i82801ix/i82801ix.h> @@ -47,7 +46,7 @@ void __weak mb_post_raminit_setup(void) /* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { sysinfo_t sysinfo; int s3resume = 0; @@ -57,8 +56,7 @@ void mainboard_romstage_entry(unsigned long bist) /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); - if (bist == 0) - enable_lapic(); + enable_lapic(); /* First, run everything needed for console output. */ i82801ix_early_init(); @@ -69,7 +67,6 @@ void mainboard_romstage_entry(unsigned long bist) mb_setup_superio(); console_init(); - report_bist_failure(bist); reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 8d7de45149..e184f789d0 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -27,7 +27,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include "raminit.h" #include "pineview.h" @@ -48,14 +47,13 @@ __weak void mb_pirq_setup(void) #define LPC_DEV PCI_DEV(0x0, 0x1f, 0x0) -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { u8 spd_addrmap[4] = {}; int boot_path, cbmem_was_initted; int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Enable GPIOs */ pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); @@ -63,9 +61,6 @@ void mainboard_romstage_entry(unsigned long bist) setup_pch_gpios(&mainboard_gpio_map); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - enable_smbus(); /* Perform some early chipset initialization required diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 2cef5f2605..bfcf79dd23 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -22,7 +22,6 @@ #include <cpu/x86/lapic.h> #include <timestamp.h> #include "sandybridge.h" -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <device/pci_def.h> #include <device/device.h> @@ -44,15 +43,14 @@ static void early_pch_reset_pmcon(void) /* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; if (MCHBAR16(SSKPD) == 0xCAFE) system_reset(); - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init(); @@ -68,9 +66,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Initialize console device(s) */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - /* Perform some early chipset initialization required * before RAM initialization can work */ |