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-rw-r--r--src/northbridge/intel/gm45/gma.c16
-rw-r--r--src/northbridge/intel/i945/gma.c6
-rw-r--r--src/northbridge/intel/nehalem/gma.c106
-rw-r--r--src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c12
-rw-r--r--src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c12
-rw-r--r--src/northbridge/intel/x4x/gma.c8
6 files changed, 80 insertions, 80 deletions
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index c060bb0be7..24046712b4 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -109,7 +109,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
hfront_porch = mode->hso;
vfront_porch = mode->vso;
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
@@ -263,7 +263,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
| (vactive - 1));
write32(mmio + PF_CTL(0), 0);
@@ -281,7 +281,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
@@ -307,7 +307,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
memset((void *) lfb, 0,
edid->x_resolution * edid->y_resolution * 4);
set_vbe_mode_info_valid(edid, lfb);
@@ -390,7 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
vfront_porch = mode->vso;
target_frequency = mode->pixel_clock;
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
@@ -520,7 +520,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
| (vactive - 1));
write32(mmio + PF_CTL(0), 0);
@@ -539,7 +539,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
write32(mmio + PIPECONF(0), PIPECONF_ENABLE
| PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
@@ -569,7 +569,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
memset((void *) lfb, 0,
edid->x_resolution * edid->y_resolution * 4);
set_vbe_mode_info_valid(edid, lfb);
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 07657678b2..3c5cee5040 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -217,7 +217,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
(pixel_n + 2) / (pixel_p1 * pixel_p2));
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
/* Disable panel fitter (we're in native resolution). */
write32(mmiobase + PF_CTL(0), 0);
write32(mmiobase + PF_WIN_SZ(0), 0);
@@ -280,7 +280,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
| (vactive + bottom_border + vfront_porch - 1));
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmiobase + PIPESRC(1), ((hactive - 1) << 16)
| (vactive - 1));
} else {
@@ -359,7 +359,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
else
printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n");
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n",
(void *)pgfx, hactive * vactive * 4);
memset((void *)pgfx, 0x00, hactive * vactive * 4);
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index daa6ec4df1..0af8d6c63a 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -724,32 +724,33 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
: (2 * mode->pixel_clock);
vga_textmode_init();
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- vga_sr_write(1, 1);
- vga_sr_write(0x2, 0xf);
- vga_sr_write(0x3, 0x0);
- vga_sr_write(0x4, 0xe);
- vga_gr_write(0, 0x0);
- vga_gr_write(1, 0x0);
- vga_gr_write(2, 0x0);
- vga_gr_write(3, 0x0);
- vga_gr_write(4, 0x0);
- vga_gr_write(5, 0x0);
- vga_gr_write(6, 0x5);
- vga_gr_write(7, 0xf);
- vga_gr_write(0x10, 0x1);
- vga_gr_write(0x11, 0);
-
-
- edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
-
- write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
- write32(mmio + DSPADDR(0), 0);
- write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
- write32(mmio + DSPSURF(0), 0);
- for (i = 0; i < 0x100; i++)
- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
-#endif
+
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
+ vga_sr_write(1, 1);
+ vga_sr_write(0x2, 0xf);
+ vga_sr_write(0x3, 0x0);
+ vga_sr_write(0x4, 0xe);
+ vga_gr_write(0, 0x0);
+ vga_gr_write(1, 0x0);
+ vga_gr_write(2, 0x0);
+ vga_gr_write(3, 0x0);
+ vga_gr_write(4, 0x0);
+ vga_gr_write(5, 0x0);
+ vga_gr_write(6, 0x5);
+ vga_gr_write(7, 0xf);
+ vga_gr_write(0x10, 0x1);
+ vga_gr_write(0x11, 0);
+
+
+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
+
+ write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
+ write32(mmio + DSPADDR(0), 0);
+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
+ write32(mmio + DSPSURF(0), 0);
+ for (i = 0; i < 0x100; i++)
+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+ }
/* Find suitable divisors. */
for (candp1 = 1; candp1 <= 8; candp1++) {
@@ -883,15 +884,15 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
- write32(mmio + PF_CTL(0),0);
- write32(mmio + PF_WIN_SZ(0), 0);
-#else
- write32(mmio + PIPESRC(0), (639 << 16) | 399);
- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
-#endif
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
+ write32(mmio + PIPESRC(0), (hactive - 1) << 16 | (vactive - 1));
+ write32(mmio + PF_CTL(0), 0);
+ write32(mmio + PF_WIN_SZ(0), 0);
+ } else {
+ write32(mmio + PIPESRC(0), (639 << 16) | 399);
+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+ }
mdelay(1);
@@ -911,17 +912,18 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
-#else
- write32(mmio + CPU_VGACNTRL, 0x20298e);
-#endif
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
+ write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
+ else
+ write32(mmio + CPU_VGACNTRL, 0x20298e);
+
train_link(mmio);
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
- mdelay(1);
-#endif
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
+ write32(mmio + DSPCNTR(0),
+ DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+ mdelay(1);
+ }
write32(mmio + TRANS_HTOTAL(0),
((hactive + right_border + hblank - 1) << 16)
@@ -946,11 +948,8 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + 0x00060100, 0xb01c4000);
write32(mmio + 0x000f000c, 0xb01a2050);
mdelay(1);
- write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- | TRANS_STATE_MASK
-#endif
- );
+ write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC |
+ (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) ? TRANS_STATE_MASK : 0));
write32(mmio + PCH_LVDS,
LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21)
@@ -988,10 +987,11 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + 0x0004f04c, 0x7f7f0000);
write32(mmio + 0x0004f054, 0x0000020d);
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
- set_vbe_mode_info_valid(&edid, lfb);
-#endif
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
+ memset((void *)lfb, 0,
+ edid.x_resolution * edid.y_resolution * 4);
+ set_vbe_mode_info_valid(&edid, lfb);
+ }
}
#endif
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index bcdeaa074a..cad5078dc3 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -217,7 +217,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
u32 pixel_m2 = 1;
vga_textmode_init();
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
@@ -387,7 +387,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
write32(mmio + 0xf0008, 0);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
write32(mmio + PF_CTL(0),0);
write32(mmio + PF_WIN_SZ(0), 0);
@@ -408,7 +408,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
link_train(mmio);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE);
else
write32(mmio+CPU_VGACNTRL,0x298e);
@@ -419,7 +419,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
mdelay(1);
read32(mmio + 0x000f0014); // = 0x00000600
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
mdelay(1);
@@ -451,7 +451,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
mdelay(1);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
| TRANS_STATE_MASK);
else
@@ -490,7 +490,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
memset ((void *) lfb, 0, edid.x_resolution
* edid.y_resolution * 4);
set_vbe_mode_info_valid(&edid, lfb);
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index e39e6bc2d0..c3139a99dd 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -200,7 +200,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
: (2 * mode->pixel_clock);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
@@ -361,7 +361,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
write32(mmio + PF_CTL(0),0);
write32(mmio + PF_WIN_SZ(0), 0);
@@ -388,14 +388,14 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
else
write32(mmio + CPU_VGACNTRL, 0x20298e);
train_link(mmio);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
mdelay(1);
}
@@ -424,7 +424,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + 0x000f000c, 0x801a2350);
mdelay(1);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
| TRANS_STATE_MASK);
else
@@ -462,7 +462,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
memset ((void *) lfb, 0, edid.x_resolution
* edid.y_resolution * 4);
set_vbe_mode_info_valid(&edid, lfb);
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index f53320a040..561e776f24 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -143,7 +143,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
} else
printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode");
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
@@ -274,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
| (vactive - 1));
write32(mmio + PF_CTL(0), 0);
@@ -293,7 +293,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
write32(mmio + PIPECONF(0), PIPECONF_ENABLE
| PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
@@ -323,7 +323,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
+ if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
memset((void *) lfb, 0,
hactive * vactive * 4);
set_vbe_mode_info_valid(&edid, lfb);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 00:59:59 +0000