4 files changed, 15 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h
index 661e5f348e..580f27831b 100644
--- a/src/northbridge/amd/amdk8/amdk8_f.h
+++ b/src/northbridge/amd/amdk8/amdk8_f.h
@@ -522,7 +522,7 @@ struct sys_info {
 
 #if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \
 	((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__))
-static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
+static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 {
 
 	int i;
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 39182854eb..9a60ecc03e 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -153,6 +153,7 @@ static void disable_probes(void)
 
 }
 
+#if 0
 static void enable_apic_ext_id(u8 node)
 {
 #if CONFIG_ENABLE_APIC_EXT_ID==1
@@ -165,6 +166,7 @@ static void enable_apic_ext_id(u8 node)
 	pci_write_config32(NODE_HT(node), 0x68, val);
 #endif
 }
+#endif
 
 static void enable_routing(u8 node)
 {
@@ -378,6 +380,7 @@ static uint8_t get_linkn_first(uint8_t byte)
 	return byte;
 }
 
+#if TRY_HIGH_FIRST == 1
 static uint8_t get_linkn_last(uint8_t byte)
 {
 	if(byte & 0x02) { byte &= 0x0f; byte |= 0x00;  }
@@ -385,7 +388,9 @@ static uint8_t get_linkn_last(uint8_t byte)
 	if(byte & 0x08) { byte &= 0x0f; byte |= 0x20;  }
 	return byte>>4;
 }
+#endif
 
+#if (CONFIG_MAX_PHYSICAL_CPUS > 2) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
 static uint8_t get_linkn_last_count(uint8_t byte)
 {
 	byte &= 0x0f;
@@ -394,6 +399,7 @@ static uint8_t get_linkn_last_count(uint8_t byte)
 	if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
 	return byte>>4;
 }
+#endif
 
 static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
 {
@@ -484,10 +490,12 @@ static void setup_temp_row(u8 source, u8 dest)
 	fill_row(source,7,get_row(source,dest));
 }
 
+#if 0
 static void clear_temp_row(u8 source)
 {
 	fill_row(source, 7, DEFAULT);
 }
+#endif
 
 static void setup_remote_node(u8 node)
 {
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index b4e3d64d63..4e295d3323 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -67,10 +67,12 @@ static uint8_t ht_lookup_slave_capability(device_t dev)
 	return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format
 }
 
+#if 0
 static uint8_t ht_lookup_host_capability(device_t dev)
 {
 	return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
 }
+#endif
 
 static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
 {
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 5cd6d53688..5a82c51dc3 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -1824,12 +1824,12 @@ static void set_sysinfo_in_ram(unsigned val)
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 #else
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+static int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
 	return nvram_pos;
 }
 
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 {
 	die("No memory NVRAM loader for DQS data! Unable to restore memory state\n");
 
@@ -1837,12 +1837,14 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 }
 #endif
 
+#if CONFIG_MEM_TRAIN_SEQ == 0
 static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
 {
 	u32 dword = pci_read_config32_index_wait(dev, 0x98, index);
 
 	return s3_save_nvram_early(dword, size, nvram_pos);
 }
+#endif
 
 static int load_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
 {