3 files changed, 0 insertions, 12 deletions
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 5aa004d9eb..a0550ec3c7 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select PARALLEL_MP
 	select C_ENVIRONMENT_BOOTBLOCK
-	select NO_BOOTBLOCK_CONSOLE
 
 config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
 	def_bool n
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index e9e6f4d094..82f80ff725 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -378,8 +378,6 @@ u32 decode_tseg_size(const u8 esmramc);
 /* Romstage mainboard callbacks */
 /* Optional: Override the default LPC config. */
 void mainboard_lpc_decode(void);
-/* Optional: Initialize the superio for serial output. */
-void mainboard_superio_config(void);
 /* Optional: mainboard specific init after console init and before raminit. */
 void mainboard_pre_raminit_config(int s3_resume);
 /* Mainboard specific RCBA init. Happens after raminit. */
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c
index c11a78ab0e..479588129d 100644
--- a/src/northbridge/intel/i945/romstage.c
+++ b/src/northbridge/intel/i945/romstage.c
@@ -28,10 +28,6 @@ __weak void mainboard_lpc_decode(void)
 {
 }
 
-__weak void mainboard_superio_config(void)
-{
-}
-
 __weak void mainboard_pre_raminit_config(int s3_resume)
 {
 }
@@ -51,12 +47,7 @@ void mainboard_romstage_entry(void)
 
 	enable_lapic();
 
-	i82801gx_lpc_setup();
 	mainboard_lpc_decode();
-	mainboard_superio_config();
-
-	/* Set up the console */
-	console_init();
 
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		system_reset();