summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c25
-rw-r--r--src/northbridge/amd/pi/00630F01/northbridge.c3
-rw-r--r--src/northbridge/amd/pi/00660F01/northbridge.c3
-rw-r--r--src/northbridge/amd/pi/00670F00/northbridge.c3
-rw-r--r--src/northbridge/amd/pi/00730F01/northbridge.c3
-rw-r--r--src/northbridge/intel/fsp_sandybridge/bootblock.c4
-rw-r--r--src/northbridge/intel/gm45/bootblock.c4
-rw-r--r--src/northbridge/intel/haswell/bootblock.c4
-rw-r--r--src/northbridge/intel/i5000/bootblock.c4
-rw-r--r--src/northbridge/intel/i945/bootblock.c4
-rw-r--r--src/northbridge/intel/sandybridge/bootblock.c4
-rw-r--r--src/northbridge/via/vx900/early_vx900.c3
12 files changed, 29 insertions, 35 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 5634441eb8..cc2e6f923b 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -740,19 +740,18 @@ static void amdfam10_domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
- if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) {
- struct resource *res = new_resource(dev, 0xc0010058);
- res->base = CONFIG_MMCONF_BASE_ADDRESS;
- res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */
- res->align = log2(res->size);
- res->gran = log2(res->size);
- res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */
- res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
- /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
- ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);
- }
+ /* We have MMCONF_SUPPORT, create the resource window. */
+ struct resource *res = new_resource(dev, 0xc0010058);
+ res->base = CONFIG_MMCONF_BASE_ADDRESS;
+ res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */
+ res->align = log2(res->size);
+ res->gran = log2(res->size);
+ res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */
+ res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
+ ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);
if (is_fam15h()) {
enable_cc6 = 0;
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index fb115ff7b2..4872db0f68 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -335,8 +335,7 @@ static void read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
- if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
- enable_mmconf_resource(dev);
+ enable_mmconf_resource(dev);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 115d760706..4c1254c0fe 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -330,8 +330,7 @@ static void read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
- if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
- enable_mmconf_resource(dev);
+ enable_mmconf_resource(dev);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c
index ce0dde3e5c..9a39410f49 100644
--- a/src/northbridge/amd/pi/00670F00/northbridge.c
+++ b/src/northbridge/amd/pi/00670F00/northbridge.c
@@ -330,8 +330,7 @@ static void read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
- if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
- enable_mmconf_resource(dev);
+ enable_mmconf_resource(dev);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 5b837218ce..44f91e2328 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -338,8 +338,7 @@ static void read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
- if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
- enable_mmconf_resource(dev);
+ enable_mmconf_resource(dev);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
diff --git a/src/northbridge/intel/fsp_sandybridge/bootblock.c b/src/northbridge/intel/fsp_sandybridge/bootblock.c
index 1c1d49214b..508afaafb7 100644
--- a/src/northbridge/intel/fsp_sandybridge/bootblock.c
+++ b/src/northbridge/intel/fsp_sandybridge/bootblock.c
@@ -9,12 +9,12 @@ static void bootblock_northbridge_init(void)
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+ * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index 10c64e9021..76ed1a0ad5 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -10,12 +10,12 @@ static void bootblock_northbridge_init(void)
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config accesses.
+ * CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 743007e157..efd3beaab9 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -9,12 +9,12 @@ static void bootblock_northbridge_init(void)
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+ * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/northbridge/intel/i5000/bootblock.c b/src/northbridge/intel/i5000/bootblock.c
index eabbee6d63..ff7513a402 100644
--- a/src/northbridge/intel/i5000/bootblock.c
+++ b/src/northbridge/intel/i5000/bootblock.c
@@ -4,12 +4,12 @@ static void bootblock_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+ * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 4571446cae..d837122e6b 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -9,12 +9,12 @@ static void bootblock_northbridge_init(void)
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+ * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index 1c1d49214b..508afaafb7 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -9,12 +9,12 @@ static void bootblock_northbridge_init(void)
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+ * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c
index eb5c79c9f9..6e1bc23cae 100644
--- a/src/northbridge/via/vx900/early_vx900.c
+++ b/src/northbridge/via/vx900/early_vx900.c
@@ -40,14 +40,13 @@ void vx900_enable_pci_config_space(void)
* accessed */
pci_io_write_config8(HOST_CTR, 0x4f, 0x01);
-#if CONFIG_MMCONF_SUPPORT
/* COOL, now enable MMCONF */
u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60);
reg8 |= 3;
pci_io_write_config8(TRAF_CTR, 0x60, reg8);
+
reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28;
pci_io_write_config8(TRAF_CTR, 0x61, reg8);
-#endif
}
/**
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 04:21:34 +0000