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-rw-r--r--src/northbridge/intel/nehalem/finalize.c2
-rw-r--r--src/northbridge/intel/nehalem/nehalem.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c
index 401d9ecb99..72baa4869b 100644
--- a/src/northbridge/intel/nehalem/finalize.c
+++ b/src/northbridge/intel/nehalem/finalize.c
@@ -24,7 +24,7 @@
#define PCI_DEV_SNB PCI_DEV(0, 0, 0)
-void intel_sandybridge_finalize_smm(void)
+void intel_nehalem_finalize_smm(void)
{
pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index b90e5a910d..2218433b7d 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -593,7 +593,7 @@ struct ied_header {
#define PCI_DEVICE_ID_IB 0x0154
#ifdef __SMM__
-void intel_sandybridge_finalize_smm(void);
+void intel_nehalem_finalize_smm(void);
#else /* !__SMM__ */
int bridge_silicon_revision(void);
void nehalem_early_initialization(int chipset_type);