3 files changed, 0 insertions, 23 deletions
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index f6d14e0bd2..c738de7916 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -62,15 +62,6 @@ static const struct pci_driver i810e_northbridge_driver __pci_driver = {
 	.device = 0x7124,
 };
 
-int add_northbridge_resources(struct lb_memory *mem)
-{
-	printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
-	lb_add_memory_range(mem, LB_MEM_RESERVED,
-		uma_memory_base, uma_memory_size);
-
-	return 0;
-}
-
 /* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
  * Note that 2 is a value which the DRP should never be programmed to.
  * Some size values appear twice, due to single-sided vs dual-sided banks.
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
index 649a203aca..4951c4f617 100644
--- a/src/northbridge/intel/i82830/northbridge.c
+++ b/src/northbridge/intel/i82830/northbridge.c
@@ -52,15 +52,6 @@ static const struct pci_driver northbridge_driver __pci_driver = {
 	.device = 0x3575,
 };
 
-int add_northbridge_resources(struct lb_memory *mem)
-{
-	printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
-	lb_add_memory_range(mem, LB_MEM_RESERVED,
-		uma_memory_base, uma_memory_size);
-
-	return 0;
-}
-
 #if CONFIG_WRITE_HIGH_TABLES
 #include <cbmem.h>
 #endif
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 2d948eaaef..b447d52dab 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -61,11 +61,6 @@ int bridge_silicon_revision(void)
 static const int legacy_hole_base_k = 0xa0000 / 1024;
 static const int legacy_hole_size_k = 384;
 
-int add_northbridge_resources(struct lb_memory *mem)
-{
-	return 0;
-}
-
 void cbmem_post_handling(void)
 {
 	update_mrc_cache();