2 files changed, 52 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 1255cac5d6..5e28336b0c 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -127,11 +127,21 @@
 #define DMILCTL		0x088	/* 16bit */
 #define DMILSTS		0x08a	/* 16bit */
 
+#define DMILCTL2	0x098	/* 16bit */
+
 #define DMICTL1		0x0f0	/* 32bit */
 #define DMICTL2		0x0fc	/* 32bit */
 
+#define DMIUESTS	0x1c4	/* 32bit */
+#define DMICESTS	0x1d0	/* 32bit */
+
 #define DMICC		0x208	/* 32bit */
 
+#define DMIL0SLAT	0x22c	/* 32bit */
+#define DMILLTC		0x238	/* 32bit */
+
+#define DMI_AFE_PM_TMR	0xc28	/* 32bit */
+
 #define DMIDRCCFG	0xeb4	/* 32bit */
 
 #ifndef __ASSEMBLER__
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index ef7742e523..5c9ef744b1 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -418,10 +418,52 @@ static void disable_devices(void)
 	pci_write_config32(host_dev, DEVEN, deven);
 }
 
+static void northbridge_dmi_init(void)
+{
+	const bool is_haswell_h = !CONFIG(INTEL_LYNXPOINT_LP);
+
+	u16 reg16;
+	u32 reg32;
+
+	/* Steps prior to DMI ASPM */
+	if (is_haswell_h) {
+		/* Configure DMI De-Emphasis */
+		reg16 = DMIBAR16(DMILCTL2);
+		reg16 |= (1 << 6);	/* 0b: -6.0 dB, 1b: -3.5 dB */
+		DMIBAR16(DMILCTL2) = reg16;
+
+		reg32 = DMIBAR32(DMIL0SLAT);
+		reg32 |= (1 << 31);
+		DMIBAR32(DMIL0SLAT) = reg32;
+
+		reg32 = DMIBAR32(DMILLTC);
+		reg32 |= (1 << 29);
+		DMIBAR32(DMILLTC) = reg32;
+
+		reg32 = DMIBAR32(DMI_AFE_PM_TMR);
+		reg32 &= ~0x1f;
+		reg32 |= 0x13;
+		DMIBAR32(DMI_AFE_PM_TMR) = reg32;
+	}
+
+	/* Clear error status bits */
+	DMIBAR32(DMIUESTS) = 0xffffffff;
+	DMIBAR32(DMICESTS) = 0xffffffff;
+
+	if (is_haswell_h) {
+		/* Enable ASPM L0s and L1 on SA link, should happen before PCH link */
+		reg16 = DMIBAR16(DMILCTL);
+		reg16 |= (1 << 1) | (1 << 0);
+		DMIBAR16(DMILCTL) = reg16;
+	}
+}
+
 static void northbridge_init(struct device *dev)
 {
 	u8 bios_reset_cpl, pair;
 
+	northbridge_dmi_init();
+
 	/* Enable Power Aware Interrupt Routing. */
 	pair = MCHBAR8(INTRDIRCTL);
 	pair &= ~0x7;	/* Clear 2:0 */