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-rw-r--r--src/northbridge/amd/amdfam10/amdfam10.h2
-rw-r--r--src/northbridge/amd/amdht/comlib.c4
-rw-r--r--src/northbridge/amd/amdht/comlib.h2
-rw-r--r--src/northbridge/amd/amdht/ht_wrapper.c2
-rw-r--r--src/northbridge/amd/amdk8/raminit_f_dqs.c2
-rw-r--r--src/northbridge/amd/amdmct/mct/mctmtr_d.c4
-rw-r--r--src/northbridge/amd/gx2/chipsetinit.c2
-rw-r--r--src/northbridge/intel/i855pm/raminit.c2
-rw-r--r--src/northbridge/motorola/mpc107/Config.lb2
-rw-r--r--src/northbridge/motorola/mpc107/mpc107_northbridge.c2
-rw-r--r--src/northbridge/via/vt8601/northbridge.c2
-rw-r--r--src/northbridge/via/vt8623/northbridge.c4
-rw-r--r--src/northbridge/via/vt8623/raminit.c2
13 files changed, 16 insertions, 16 deletions
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 029e5e7a6d..d3fb11e349 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1019,7 +1019,7 @@ struct nodes_info_t {
u32 up_planes; // down planes will be [up_planes, planes)
} __attribute__((packed));
-/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by linuxbios_car and linuxbios_ram stage. and linuxbios_ram may be running at 64bit later.*/
+/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/
#if CONFIG_AMDMCT == 0
//#define MEM_CS_COPY 1
diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c
index e9abb0bb06..249388b04a 100644
--- a/src/northbridge/amd/amdht/comlib.c
+++ b/src/northbridge/amd/amdht/comlib.c
@@ -206,14 +206,14 @@ u32 CALLCONV AmdRotateLeft(u32 value, u8 size, u32 count)
void CALLCONV AmdPCIRead(SBDFO loc, u32 *Value)
{
- /* Use LinuxBIOS PCI functions */
+ /* Use coreboot PCI functions */
*Value = pci_read_config32((loc & 0xFFFFF000), SBDFO_OFF(loc));
}
void CALLCONV AmdPCIWrite(SBDFO loc, u32 *Value)
{
- /* Use LinuxBIOS PCI functions */
+ /* Use coreboot PCI functions */
pci_write_config32((loc & 0xFFFFF000), SBDFO_OFF(loc), *Value);
}
diff --git a/src/northbridge/amd/amdht/comlib.h b/src/northbridge/amd/amdht/comlib.h
index a8b7b5c1c9..1f6fc0f9fb 100644
--- a/src/northbridge/amd/amdht/comlib.h
+++ b/src/northbridge/amd/amdht/comlib.h
@@ -26,7 +26,7 @@
#include "porting.h"
-/* include LinuxBIOS pci functions */
+/* include coreboot pci functions */
#include <device/pci_def.h>
#include <device/pci_ids.h>
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index 09953da2c4..aaf67a47a7 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -124,7 +124,7 @@ void getAmdTopolist(u8 ***p)
/**
* void amd_ht_init(struct sys_info *sysinfo)
*
- * AMD HT init LinuxBIOS wrapper
+ * AMD HT init coreboot wrapper
*
*/
void amd_ht_init(struct sys_info *sysinfo)
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 757acba7d7..1b5af6864f 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -2003,7 +2003,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy
train_ram(nodeid, sysinfo, sysinfox);
#else
/* Can copy dqs_timing to ap cache and run from cache?
- * we need linuxbios_ap_car.rom? and treat it as linuxbios_ram.rom for ap ?
+ * we need coreboot_ap_car.rom? and treat it as coreboot_ram.rom for ap ?
*/
copy_and_run_ap_code_in_car(retcall);
// will go back by jump
diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
index c0839d2a88..d39bfcc8b2 100644
--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
@@ -75,7 +75,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
Set default values for CPU registers
======================================================================*/
- /* NOTE : For LinuxBIOS, we don't need to set mtrr enables here because
+ /* NOTE : For coreboot, we don't need to set mtrr enables here because
they are still enable from cache_as_ram.inc */
addr = 0x250;
@@ -88,7 +88,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
/*======================================================================
Set variable MTRR values
======================================================================*/
- /* NOTE: for LinuxBIOS change from 0x200 to 0x204: LinuxBIOS is using
+ /* NOTE: for coreboot change from 0x200 to 0x204: coreboot is using
0x200, 0x201 for [1M, CONFIG_TOP_MEM)
0x202, 0x203 for ROM Caching
*/
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c
index dcbfdb99b6..4751886a45 100644
--- a/src/northbridge/amd/gx2/chipsetinit.c
+++ b/src/northbridge/amd/gx2/chipsetinit.c
@@ -295,7 +295,7 @@ chipsetinit (struct northbridge_amd_gx2_config *nb){
outb( P80_CHIPSET_INIT, 0x80);
ChipsetGeodeLinkInit();
#if 0
- /* we hope NEVER to be in linuxbios when S3 resumes
+ /* we hope NEVER to be in coreboot when S3 resumes
if (! IsS3Resume()) */
{
struct acpiinit *aci = acpi_init_table;
diff --git a/src/northbridge/intel/i855pm/raminit.c b/src/northbridge/intel/i855pm/raminit.c
index 07dac67a73..9a0f7c08d9 100644
--- a/src/northbridge/intel/i855pm/raminit.c
+++ b/src/northbridge/intel/i855pm/raminit.c
@@ -1358,7 +1358,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
}
- /* I have finally seen ram bad enough to cause LinuxBIOS
+ /* I have finally seen ram bad enough to cause coreboot
* to die in mysterious ways, before booting up far
* enough to run a memory tester. This code attempts
* to catch this blatantly bad ram, with a spot check.
diff --git a/src/northbridge/motorola/mpc107/Config.lb b/src/northbridge/motorola/mpc107/Config.lb
index 78fc99e85f..83e7b3d0b3 100644
--- a/src/northbridge/motorola/mpc107/Config.lb
+++ b/src/northbridge/motorola/mpc107/Config.lb
@@ -1,5 +1,5 @@
#
-# Objects linked with linuxbios
+# Objects linked with coreboot
#
config chip.h
diff --git a/src/northbridge/motorola/mpc107/mpc107_northbridge.c b/src/northbridge/motorola/mpc107/mpc107_northbridge.c
index 7dcf7c89f8..7e692f039d 100644
--- a/src/northbridge/motorola/mpc107/mpc107_northbridge.c
+++ b/src/northbridge/motorola/mpc107/mpc107_northbridge.c
@@ -36,7 +36,7 @@ static void pci_domain_read_resources(device_t dev)
/*
* pci_domain_set_resources creates memory resources describing the
* fixed memory on the system. This is not actually used anywhere
- * except when the linuxbios table is generated.
+ * except when the coreboot table is generated.
*/
static void pci_domain_set_resources(device_t dev)
{
diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index 89f0874b35..76d93f0ddb 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -121,7 +121,7 @@ static void pci_domain_set_resources(device_t dev)
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
- * We take the highest one to cover for once and future linuxbios
+ * We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index bd128b9cc9..e2bab04afe 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -158,7 +158,7 @@ static void vga_init(device_t dev)
#else
- /* code to make vga init run in real mode - does work but against the current Linuxbios philosophy */
+ /* code to make vga init run in real mode - does work but against the current coreboot philosophy */
printk_debug("INSTALL REAL-MODE IDT\n");
setup_realmode_idt();
printk_debug("DO THE VGA BIOS\n");
@@ -293,7 +293,7 @@ static void pci_domain_set_resources(device_t dev)
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
- * We take the highest one to cover for once and future linuxbios
+ * We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c
index 5508e3e659..c543428216 100644
--- a/src/northbridge/via/vt8623/raminit.c
+++ b/src/northbridge/via/vt8623/raminit.c
@@ -28,7 +28,7 @@
256 Mb 266Mhz 2 Bank (i.e. double sided)
512 Mb 266Mhz 2 Bank (i.e. double sided)
*/
-/* ported and enhanced from assembler level code in Linuxbios v1 */
+/* ported and enhanced from assembler level code in coreboot v1 */
#include <cpu/x86/mtrr.h>
#include "raminit.h"
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 12:08:16 +0000