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-rw-r--r--src/northbridge/intel/haswell/Kconfig9
-rw-r--r--src/northbridge/intel/haswell/early_init.c23
2 files changed, 26 insertions, 6 deletions
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 84be33df4e..04ab373ce2 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -78,6 +78,15 @@ config MRC_FILE
The path and filename of the file to use as System Agent
binary.
+config HASWELL_HIDE_PEG_FROM_MRC
+ bool "Hide PEG devices from MRC to work around hardcoded MRC behavior"
+ default y
+ help
+ If set, hides all PEG devices from MRC. This allows the iGPU
+ to be used even when a dedicated graphics card is present.
+ However, it prevents MRC from programming PEG AFE registers,
+ which can make PEG devices unstable. When unsure, choose N.
+
config PRE_GRAPHICS_DELAY
int "Graphics initialization delay in ms"
default 0
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 9db6a9d0de..79cc27724c 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -84,13 +84,24 @@ static void start_peg2_link_training(const pci_devfn_t dev)
printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
/*
- * Hide the PEG device while the MRC runs. This is because the MRC makes
- * configurations that are not ideal if it sees a VGA device in a PEG slot,
- * and it locks registers preventing changes to these configurations.
+ * The MRC will perform PCI enumeration, and if it detects a VGA
+ * device in a PEG slot, it will disable the IGD and not reserve
+ * any memory for it. Since the memory map is locked by the time
+ * MRC finishes, the IGD can't be enabled afterwards. Wonderful.
+ *
+ * If one really wants to enable the Intel iGPU as primary, hide
+ * all PEG devices during MRC execution. This will trick the MRC
+ * into thinking there aren't any, and will enable the IGD. Note
+ * that PEG AFE settings will not be programmed, which may cause
+ * stability problems at higher PCIe link speeds. The most ideal
+ * way to fix this problem for good is to implement native init.
*/
- pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0);
- peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
- printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
+ if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) {
+ pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0);
+ peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
+ printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n",
+ PCI_FUNC(PCI_DEV2DEVFN(dev)));
+ }
}
void haswell_unhide_peg(void)