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-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c94
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.h1
-rw-r--r--src/northbridge/intel/sandybridge/raminit_iosav.c97
3 files changed, 99 insertions, 93 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 68281dd582..4ba2f0de82 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1428,99 +1428,7 @@ static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank)
wait_for_iosav(channel);
- const struct iosav_ssq rd_sequence[] = {
- /* DRAM command PREA */
- [0] = {
- .sp_cmd_ctrl = {
- .command = IOSAV_PRE,
- .ranksel_ap = 1,
- },
- .subseq_ctrl = {
- .cmd_executions = 1,
- .cmd_delay_gap = 3,
- .post_ssq_wait = ctrl->tRP,
- .data_direction = SSQ_NA,
- },
- .sp_cmd_addr = {
- .address = 1024,
- .rowbits = 6,
- .bank = 0,
- .rank = slotrank,
- },
- .addr_update = {
- .addr_wrap = 18,
- },
- },
- /* DRAM command ACT */
- [1] = {
- .sp_cmd_ctrl = {
- .command = IOSAV_ACT,
- .ranksel_ap = 1,
- },
- .subseq_ctrl = {
- .cmd_executions = 8,
- .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1),
- .post_ssq_wait = ctrl->CAS,
- .data_direction = SSQ_NA,
- },
- .sp_cmd_addr = {
- .address = 0,
- .rowbits = 6,
- .bank = 0,
- .rank = slotrank,
- },
- .addr_update = {
- .inc_bank = 1,
- .addr_wrap = 18,
- },
- },
- /* DRAM command RD */
- [2] = {
- .sp_cmd_ctrl = {
- .command = IOSAV_RD,
- .ranksel_ap = 1,
- },
- .subseq_ctrl = {
- .cmd_executions = 500,
- .cmd_delay_gap = 4,
- .post_ssq_wait = MAX(ctrl->tRTP, 8),
- .data_direction = SSQ_RD,
- },
- .sp_cmd_addr = {
- .address = 0,
- .rowbits = 0,
- .bank = 0,
- .rank = slotrank,
- },
- .addr_update = {
- .inc_addr_8 = 1,
- .addr_wrap = 18,
- },
- },
- /* DRAM command PREA */
- [3] = {
- .sp_cmd_ctrl = {
- .command = IOSAV_PRE,
- .ranksel_ap = 1,
- },
- .subseq_ctrl = {
- .cmd_executions = 1,
- .cmd_delay_gap = 3,
- .post_ssq_wait = ctrl->tRP,
- .data_direction = SSQ_NA,
- },
- .sp_cmd_addr = {
- .address = 1024,
- .rowbits = 6,
- .bank = 0,
- .rank = slotrank,
- },
- .addr_update = {
- .addr_wrap = 18,
- },
- },
- };
- iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence));
+ iosav_write_prea_act_read_sequence(ctrl, channel, slotrank);
/* Execute command queue */
iosav_run_once(channel);
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index c1fb10b207..44f4768a95 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -253,6 +253,7 @@ void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32
void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap);
void iosav_write_read_mpr_sequence(
int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2);
+void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank);
void iosav_write_jedec_write_leveling_sequence(
ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg);
void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank,
diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c
index 25f5ae705d..d83dfd8e9a 100644
--- a/src/northbridge/intel/sandybridge/raminit_iosav.c
+++ b/src/northbridge/intel/sandybridge/raminit_iosav.c
@@ -199,6 +199,103 @@ void iosav_write_read_mpr_sequence(
iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence));
}
+void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank)
+{
+ const struct iosav_ssq sequence[] = {
+ /* DRAM command PREA */
+ [0] = {
+ .sp_cmd_ctrl = {
+ .command = IOSAV_PRE,
+ .ranksel_ap = 1,
+ },
+ .subseq_ctrl = {
+ .cmd_executions = 1,
+ .cmd_delay_gap = 3,
+ .post_ssq_wait = ctrl->tRP,
+ .data_direction = SSQ_NA,
+ },
+ .sp_cmd_addr = {
+ .address = 1024,
+ .rowbits = 6,
+ .bank = 0,
+ .rank = slotrank,
+ },
+ .addr_update = {
+ .addr_wrap = 18,
+ },
+ },
+ /* DRAM command ACT */
+ [1] = {
+ .sp_cmd_ctrl = {
+ .command = IOSAV_ACT,
+ .ranksel_ap = 1,
+ },
+ .subseq_ctrl = {
+ .cmd_executions = 8,
+ .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1),
+ .post_ssq_wait = ctrl->CAS,
+ .data_direction = SSQ_NA,
+ },
+ .sp_cmd_addr = {
+ .address = 0,
+ .rowbits = 6,
+ .bank = 0,
+ .rank = slotrank,
+ },
+ .addr_update = {
+ .inc_bank = 1,
+ .addr_wrap = 18,
+ },
+ },
+ /* DRAM command RD */
+ [2] = {
+ .sp_cmd_ctrl = {
+ .command = IOSAV_RD,
+ .ranksel_ap = 1,
+ },
+ .subseq_ctrl = {
+ .cmd_executions = 500,
+ .cmd_delay_gap = 4,
+ .post_ssq_wait = MAX(ctrl->tRTP, 8),
+ .data_direction = SSQ_RD,
+ },
+ .sp_cmd_addr = {
+ .address = 0,
+ .rowbits = 0,
+ .bank = 0,
+ .rank = slotrank,
+ },
+ .addr_update = {
+ .inc_addr_8 = 1,
+ .addr_wrap = 18,
+ },
+ },
+ /* DRAM command PREA */
+ [3] = {
+ .sp_cmd_ctrl = {
+ .command = IOSAV_PRE,
+ .ranksel_ap = 1,
+ },
+ .subseq_ctrl = {
+ .cmd_executions = 1,
+ .cmd_delay_gap = 3,
+ .post_ssq_wait = ctrl->tRP,
+ .data_direction = SSQ_NA,
+ },
+ .sp_cmd_addr = {
+ .address = 1024,
+ .rowbits = 6,
+ .bank = 0,
+ .rank = slotrank,
+ },
+ .addr_update = {
+ .addr_wrap = 18,
+ },
+ },
+ };
+ iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence));
+}
+
void iosav_write_jedec_write_leveling_sequence(
ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg)
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 05:57:49 +0000