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-rw-r--r--src/northbridge/amd/amdk8/raminit.c12
-rw-r--r--src/northbridge/amd/amdk8/raminit_f.c6
-rw-r--r--src/northbridge/intel/gm45/raminit.c2
-rw-r--r--src/northbridge/intel/i3100/raminit_ep80579.c10
-rw-r--r--src/northbridge/intel/nehalem/raminit.c4
-rw-r--r--src/northbridge/via/vx800/timing_setting.c19
-rw-r--r--src/northbridge/via/vx900/raminit_ddr3.c22
7 files changed, 36 insertions, 39 deletions
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 7e42e94a3c..f3194503a9 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -1712,7 +1712,7 @@ static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_p
if ((value == 0) || (value == 0xff)) {
value = param->tRC;
}
- clocks = ((value << 1) + param->divisor - 1)/param->divisor;
+ clocks = CEIL_DIV((value << 1), param->divisor);
if (clocks < DTL_TRC_MIN) {
clocks = DTL_TRC_MIN;
}
@@ -1741,7 +1741,7 @@ static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_
if ((value == 0) || (value == 0xff)) {
value = param->tRFC;
}
- clocks = ((value << 1) + param->divisor - 1)/param->divisor;
+ clocks = CEIL_DIV((value << 1), param->divisor);
if (clocks < DTL_TRFC_MIN) {
clocks = DTL_TRFC_MIN;
}
@@ -1767,7 +1767,7 @@ static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_
int value;
value = spd_read_byte(ctrl->channel0[i], 29);
if (value < 0) return -1;
- clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1);
+ clocks = CEIL_DIV(value, (param->divisor << 1));
if (clocks < DTL_TRCD_MIN) {
clocks = DTL_TRCD_MIN;
}
@@ -1792,7 +1792,7 @@ static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_
int value;
value = spd_read_byte(ctrl->channel0[i], 28);
if (value < 0) return -1;
- clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1);
+ clocks = CEIL_DIV(value, (param->divisor << 1));
if (clocks < DTL_TRRD_MIN) {
clocks = DTL_TRRD_MIN;
}
@@ -1817,7 +1817,7 @@ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_
int value;
value = spd_read_byte(ctrl->channel0[i], 30);
if (value < 0) return -1;
- clocks = ((value << 1) + param->divisor - 1)/param->divisor;
+ clocks = CEIL_DIV((value << 1), param->divisor);
if (clocks < DTL_TRAS_MIN) {
clocks = DTL_TRAS_MIN;
}
@@ -1842,7 +1842,7 @@ static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_p
int value;
value = spd_read_byte(ctrl->channel0[i], 27);
if (value < 0) return -1;
- clocks = (value + (param->divisor << 1) - 1)/(param->divisor << 1);
+ clocks = CEIL_DIV(value, (param->divisor << 1));
if (clocks < DTL_TRP_MIN) {
clocks = DTL_TRP_MIN;
}
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 36e0527dd8..b8417a6203 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1973,7 +1973,7 @@ static int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
value *= 10;
printk_raminit("update_dimm_Trc: tRC final value = %i\n", value);
- clocks = (value + param->divisor - 1)/param->divisor;
+ clocks = CEIL_DIV(value, param->divisor);
printk_raminit("update_dimm_Trc: clocks = %i\n", clocks);
if (clocks < DTL_TRC_MIN) {
@@ -2069,7 +2069,7 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me
value = spd_read_byte(spd_device, SPD_TT); //already in 1/4 ns
if (value < 0) return -1;
value *=10;
- clocks = (value + param->divisor -1)/param->divisor;
+ clocks = CEIL_DIV(value, param->divisor);
if (clocks < TT_MIN) {
clocks = TT_MIN;
}
@@ -2123,7 +2123,7 @@ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_
value *= 10;
printk_raminit("update_dimm_Tras: 1 value= %08x\n", value);
- clocks = (value + param->divisor - 1)/param->divisor;
+ clocks = CEIL_DIV(value, param->divisor);
printk_raminit("update_dimm_Tras: divisor= %08x\n", param->divisor);
printk_raminit("update_dimm_Tras: clocks= %08x\n", clocks);
if (clocks < DTL_TRAS_MIN) {
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 0636d9f9f2..1f667609f4 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -362,7 +362,7 @@ static void collect_ddr3(spdinfo_t *const config)
}
}
-#define ROUNDUP_DIV(val, by) (((val) + (by) - 1) / (by))
+#define ROUNDUP_DIV(val, by) CEIL_DIV(val, by)
#define ROUNDUP_DIV_THIS(val, by) val = ROUNDUP_DIV(val, by)
static fsb_clock_t read_fsb_clock(void)
{
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 90c1005b4c..962b7aa86b 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -335,7 +335,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACT_TO_ACT_AUTO_REFRESH);
val <<= 2; /* convert to 1/4 ns */
val += byte40rem[(val1 >> 4) & 0x7];
- val = (val + ci - 1) / ci + 1; /* convert to cycles */
+ val = CEIL_DIV(val, ci) + 1; /* convert to cycles */
if (trc < val)
trc = val;
val = spd_read_byte(ctrl->channel0[i], SPD_MIN_AUTO_REFRESH_TO_ACT);
@@ -343,7 +343,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
if (val1 & 0x01)
val += 1024;
val += byte40rem[(val1 >> 1) & 0x7];
- val = (val + ci - 1) / ci; /* convert to cycles */
+ val = CEIL_DIV(val, ci); /* convert to cycles */
if (trfc < val)
trfc = val;
}
@@ -360,15 +360,15 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
continue;
val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
val <<= 2; /* convert to 1/4 ns */
- val = (val + ci - 1) / ci; /* convert to cycles */
+ val = CEIL_DIV(val, ci); /* convert to cycles */
if (tras < val)
tras = val;
val = spd_read_byte(ctrl->channel0[i], SPD_INT_READ_TO_PRECHARGE_DELAY);
- val = (val + ci - 1) / ci; /* convert to cycles */
+ val = CEIL_DIV(val, ci); /* convert to cycles */
if (trtp < val)
trtp = val;
val = spd_read_byte(ctrl->channel0[i], SPD_INT_WRITE_TO_READ_DELAY);
- val = (val + ci - 1) / ci; /* convert to cycles */
+ val = CEIL_DIV(val, ci); /* convert to cycles */
if (twtr < val)
twtr = val;
}
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 761dc527bf..6673b5a846 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -647,7 +647,7 @@ static void calculate_timings(struct raminfo *info)
break;
}
}
- min_cas_latency = (cas_latency_time + cycletime - 1) / cycletime;
+ min_cas_latency = CEIL_DIV(cas_latency_time, cycletime);
cas_latency = 0;
while (supported_cas_latencies) {
cas_latency = find_highest_bit_set(supported_cas_latencies) + 3;
@@ -3337,7 +3337,7 @@ static unsigned gcd(unsigned a, unsigned b)
static inline int div_roundup(int a, int b)
{
- return (a + b - 1) / b;
+ return CEIL_DIV(a, b);
}
static unsigned lcm(unsigned a, unsigned b)
diff --git a/src/northbridge/via/vx800/timing_setting.c b/src/northbridge/via/vx800/timing_setting.c
index df903049b9..3bd45e40ae 100644
--- a/src/northbridge/via/vx800/timing_setting.c
+++ b/src/northbridge/via/vx800/timing_setting.c
@@ -117,8 +117,7 @@ void SetTrp(DRAM_SYS_ATTR * DramAttr)
/*Calculate clock,this value should be 2T,3T,4T,5T */
}
Tmp =
- (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) -
- 1) / ((DramAttr->DramCyc) << 2));
+ (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2);
PRINT_DEBUG_MEM("Trp = ");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -168,8 +167,7 @@ void SetTrcd(DRAM_SYS_ATTR * DramAttr)
}
/*Calculate clock,this value should be 2T,3T,4T,5T */
Tmp =
- (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) -
- 1) / ((DramAttr->DramCyc) << 2));
+ (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2);
PRINT_DEBUG_MEM("Trcd =");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -213,7 +211,7 @@ void SetTras(DRAM_SYS_ATTR * DramAttr)
}
/*Calculate clock,value range 5T-20T */
- Tmp = (u16) ((Max * 100 + DramAttr->DramCyc - 1) / (DramAttr->DramCyc));
+ Tmp = (u16) CEIL_DIV((Max * 100), DramAttr->DramCyc);
PRINT_DEBUG_MEM("Tras =");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -288,7 +286,7 @@ void SetTrfc(DRAM_SYS_ATTR * DramAttr)
}
/*Calculate clock,value range 8T-71T */
- Tmp = (u16) ((Max + DramAttr->DramCyc - 1) / (DramAttr->DramCyc));
+ Tmp = (u16) CEIL_DIV(Max, DramAttr->DramCyc);
PRINT_DEBUG_MEM("Trfc = ");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -334,8 +332,7 @@ void SetTrrd(DRAM_SYS_ATTR * DramAttr)
/*Calculate clock,this value should be 2T,3T,4T,5T */
Tmp =
- (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) -
- 1) / ((DramAttr->DramCyc) << 2));
+ (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2);
PRINT_DEBUG_MEM("Trrd =");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -378,7 +375,7 @@ void SetTwr(DRAM_SYS_ATTR * DramAttr)
}
}
/*Calculate clock */
- Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T,3T,4T,5T
+ Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T,3T,4T,5T
PRINT_DEBUG_MEM("Twr = ");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -421,7 +418,7 @@ void SetTwtr(DRAM_SYS_ATTR * DramAttr)
}
}
/*Calculate clock */
- Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T
+ Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T
PRINT_DEBUG_MEM("Twtr =");
PRINT_DEBUG_MEM_HEX16(Tmp);
@@ -463,7 +460,7 @@ void SetTrtp(DRAM_SYS_ATTR * DramAttr)
}
}
/*Calculate clock */
- Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T
+ Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T
PRINT_DEBUG_MEM("Trtp =");
PRINT_DEBUG_MEM_HEX16(Tmp);
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index a69d6999c8..3979466bf0 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -575,7 +575,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
printram("Selected DRAM frequency: %u MHz\n", val32);
/* Find CAS and CWL latencies */
- val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tAA, ctrl->tCK);
printram("Minimum CAS latency : %uT\n", val);
/* Find lowest supported CAS latency that satisfies the minimum value */
while (!((ctrl->cas_supported >> (val - 4)) & 1)
@@ -594,30 +594,30 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc0, reg8);
/* Find tRCD */
- val = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRCD, ctrl->tCK);
printram("Selected tRCD : %uT\n", val);
reg8 = ((val - 4) & 0x7) << 4;
/* Find tRP */
- val = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRP, ctrl->tCK);
printram("Selected tRP : %uT\n", val);
reg8 |= ((val - 4) & 0x7);
pci_write_config8(MCU, 0xc1, reg8);
/* Find tRAS */
- val = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRAS, ctrl->tCK);
printram("Selected tRAS : %uT\n", val);
reg8 = ((val - 15) & 0x7) << 4;
/* Find tWR */
- ctrl->WR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK;
+ ctrl->WR = CEIL_DIV(ctrl->tWR, ctrl->tCK);
printram("Selected tWR : %uT\n", ctrl->WR);
reg8 |= ((ctrl->WR - 4) & 0x7);
pci_write_config8(MCU, 0xc2, reg8);
/* Find tFAW */
- tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK;
+ tFAW = CEIL_DIV(ctrl->tFAW, ctrl->tCK);
printram("Selected tFAW : %uT\n", tFAW);
/* Find tRRD */
- tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK;
+ tRRD = CEIL_DIV(ctrl->tRRD, ctrl->tCK);
printram("Selected tRRD : %uT\n", tRRD);
val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */
reg8 = ((val - 0) & 0x7) << 4;
@@ -625,11 +625,11 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc3, reg8);
/* Find tRTP */
- val = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRTP, ctrl->tCK);
printram("Selected tRTP : %uT\n", val);
reg8 = ((val & 0x3) << 4);
/* Find tWTR */
- val = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tWTR, ctrl->tCK);
printram("Selected tWTR : %uT\n", val);
reg8 |= ((val - 2) & 0x7);
pci_mod_config8(MCU, 0xc4, 0x3f, reg8);
@@ -642,7 +642,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
* Since we previously set RxC4[7]
*/
reg8 = pci_read_config8(MCU, 0xc5);
- val = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRFC, ctrl->tCK);
printram("Minimum tRFC : %uT\n", val);
if (val < 30) {
val = 0;
@@ -655,7 +655,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc5, reg8);
/* Where does this go??? */
- val = (ctrl->tRC + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRC, ctrl->tCK);
printram("Required tRC : %uT\n", val);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 01:09:51 +0000