diff options
Diffstat (limited to 'src/northbridge')
-rw-r--r-- | src/northbridge/intel/gm45/acpi/gm45.asl | 3 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/pcie.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/acpi/hostbridge.asl | 3 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/i945/acpi/i945.asl | 3 | ||||
-rw-r--r-- | src/northbridge/intel/i945/early_init.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/ironlake/acpi/ironlake.asl | 3 | ||||
-rw-r--r-- | src/northbridge/intel/pineview/acpi/pineview.asl | 3 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/acpi/sandybridge.asl | 3 | ||||
-rw-r--r-- | src/northbridge/intel/x4x/acpi/x4x.asl | 3 |
11 files changed, 11 insertions, 18 deletions
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 7f642194ba..8c5fb499ee 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -3,7 +3,6 @@ #include "hostbridge.asl" #include "../memmap.h" #include <southbridge/intel/i82801ix/i82801ix.h> -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -14,7 +13,7 @@ Device (PDRC) // This does not seem to work correctly yet - set values statically for // now. Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index fd7ce527a1..f2c0090ed5 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -264,7 +264,7 @@ static void setup_rcrb(const int peg_enabled) /* Link1: target port 0, component id 2 (ICH), link valid. */ DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0); - DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; /* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 9a39647c06..50a130694f 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "../haswell.h" -#include <southbridge/intel/common/rcba.h> Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI @@ -175,7 +174,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 8af6eb27f0..c2c8143be7 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -511,7 +511,7 @@ static void northbridge_topology_init(void) reg32 &= ~(0xffff << 16); reg32 |= 1 | (2 << 16); DMIBAR32(DMILE1D) = reg32; - DMIBAR64(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; reg32 = DMIBAR32(DMILE2D); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 3227c02287..f5d500b2fb 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -56,7 +56,7 @@ void mainboard_romstage_entry(void) .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, + .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 11d3b505ee..5e7f4ec454 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "../i945.h" -#include <southbridge/intel/common/rcba.h> /* Operating System Capabilities Method */ Method (_OSC, 4) @@ -38,7 +37,7 @@ Device (PDRC) //}) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index dea4f9b72b..4564ff4bbb 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -730,7 +730,7 @@ static void i945_setup_root_complex_topology(void) reg32 |= (1 << 0); DMIBAR32(DMILE1D) = reg32; - DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 73242e4503..c43b17b38f 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -2,7 +2,6 @@ #include "../ironlake.h" #include "hostbridge.asl" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 4620c4f541..2f34b0d108 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "../memmap.h" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -13,7 +12,7 @@ Device (PDRC) /* This does not seem to work correctly yet - set values statically for now. */ Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 1e47c1f21b..16bcd5480f 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "peg.asl" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) // Filled by _CRS Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 33cb7ad641..60ee615f65 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -2,7 +2,6 @@ #include "hostbridge.asl" #include "../memmap.h" -#include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) |